TY - JOUR
T1 - Obfuscating the Interconnects
T2 - Low-Cost and Resilient Full-Chip Layout Camouflaging
AU - Patnaik, Satwik
AU - Ashraf, Mohammed
AU - Sinanoglu, Ozgur
AU - Knechtel, Johann
N1 - Funding Information:
Manuscript received August 30, 2019; revised November 24, 2019 and February 28, 2020; accepted March 11, 2020. Date of publication March 17, 2020; date of current version November 20, 2020. This work was supported in part by the Army Research Office under Grant 65513-CS, in part by the Center for Cyber Security at NYU/NYU AD, and in part by the NYU AD Research Enhancement Fund under Grant RE218. The work of Satwik Patnaik was supported by the Global Ph.D. Fellowship at NYU/NYU AD. Besides, this work was carried out in part on the HPC facility at NYU AD. This article is an extension of [1]. This article was recommended by Associate Editor Y. Makris. (Corresponding author: Satwik Patnaik; Johann Knechtel.) Satwik Patnaik is with the Department of Electrical and Computer Engineering, Tandon School of Engineering, New York University, Brooklyn, NY 11201 USA (e-mail: sp4012@nyu.edu).
Publisher Copyright:
© 1982-2012 IEEE.
PY - 2020/12
Y1 - 2020/12
N2 - Layout camouflaging can protect the intellectual property of modern circuits. Most prior art, however, incurs excessive layout overheads and necessitates customization of active-device manufacturing processes, i.e., the front-end-of-line (FEOL). As a result, camouflaging has typically been applied selectively, which can ultimately undermine its resilience. Here, we propose a low-cost and generic scheme - full-chip camouflaging can be finally realized without reservations. Our scheme is based on obfuscating the interconnects, i.e., the back-end-of-line (BEOL), through design-time handling for real and dummy wires and vias. To that end, we implement custom, BEOL-centric obfuscation cells, and develop a CAD flow using industrial tools. Our scheme can be applied to any design and technology node without FEOL-level modifications. Considering its BEOL-centric nature, we advocate applying our scheme in conjunction with split manufacturing, to furthermore protect against untrusted fabs. We evaluate our scheme for various designs at the physical, DRC-clean layout level. Our scheme incurs a significantly lower cost than most of the prior art. Notably, for fully camouflaged layouts, we observe average power, performance, and area overheads of 24.96%, 19.06%, and 32.55%, respectively. We conduct a thorough security study addressing the threats (attacks) related to untrustworthy FEOL fabs (proximity attacks) and malicious end-users (SAT-based attacks). An empirical key finding is that only large-scale camouflaging schemes like ours are practically secure against powerful SAT-based attacks. Another key finding is that our scheme hinders both placement- and routing-centric proximity attacks; correct connections are reduced by 7.47times , and complexity is increased by 24.15times , respectively, for such attacks.
AB - Layout camouflaging can protect the intellectual property of modern circuits. Most prior art, however, incurs excessive layout overheads and necessitates customization of active-device manufacturing processes, i.e., the front-end-of-line (FEOL). As a result, camouflaging has typically been applied selectively, which can ultimately undermine its resilience. Here, we propose a low-cost and generic scheme - full-chip camouflaging can be finally realized without reservations. Our scheme is based on obfuscating the interconnects, i.e., the back-end-of-line (BEOL), through design-time handling for real and dummy wires and vias. To that end, we implement custom, BEOL-centric obfuscation cells, and develop a CAD flow using industrial tools. Our scheme can be applied to any design and technology node without FEOL-level modifications. Considering its BEOL-centric nature, we advocate applying our scheme in conjunction with split manufacturing, to furthermore protect against untrusted fabs. We evaluate our scheme for various designs at the physical, DRC-clean layout level. Our scheme incurs a significantly lower cost than most of the prior art. Notably, for fully camouflaged layouts, we observe average power, performance, and area overheads of 24.96%, 19.06%, and 32.55%, respectively. We conduct a thorough security study addressing the threats (attacks) related to untrustworthy FEOL fabs (proximity attacks) and malicious end-users (SAT-based attacks). An empirical key finding is that only large-scale camouflaging schemes like ours are practically secure against powerful SAT-based attacks. Another key finding is that our scheme hinders both placement- and routing-centric proximity attacks; correct connections are reduced by 7.47times , and complexity is increased by 24.15times , respectively, for such attacks.
KW - Camouflaging
KW - full-chip intellectual property protection
KW - hardware security
KW - interconnects
KW - split manufacturing
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U2 - 10.1109/TCAD.2020.2981034
DO - 10.1109/TCAD.2020.2981034
M3 - Article
AN - SCOPUS:85081964415
VL - 39
SP - 4466
EP - 4481
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SN - 0278-0070
IS - 12
M1 - 9039593
ER -