On Improving the Security of Logic Locking

Muhammad Yasin; Jeyavijayan Jv Rajendran; Ozgur Sinanoglu; Ramesh Karri

doi:10.1109/TCAD.2015.2511144

On Improving the Security of Logic Locking

Muhammad Yasin, Jeyavijayan Jv Rajendran, Ozgur Sinanoglu, Ramesh Karri

Research output: Contribution to journal › Article › peer-review

Abstract

Due to globalization of integrated circuit (IC) design flow, rogue elements in the supply chain can pirate ICs, overbuild ICs, and insert hardware Trojans. EPIC locks the design by randomly inserting additional gates; only a correct key makes the design to produce correct outputs. We demonstrate that an attacker can decipher the locked netlist, in a time linear to the number of keys, by sensitizing the key-bits to the output. We then develop techniques to fix this vulnerability and make an attacker's effort truly exponential in the number of inserted keys. We introduce a new security metric and a method to deliver strong logic locking.

Original language	English (US)
Article number	7362173
Pages (from-to)	1411-1424
Number of pages	14
Journal	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume	35
Issue number	9
DOIs	https://doi.org/10.1109/TCAD.2015.2511144
State	Published - Sep 2016

Keywords

Design for trust
IP protection
hardware security
intellectual property (IP) piracy
logic encryption

ASJC Scopus subject areas

Software
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

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10.1109/TCAD.2015.2511144

Cite this

@article{462bb3e5543a411f8cede910625caf7f,

title = "On Improving the Security of Logic Locking",

abstract = "Due to globalization of integrated circuit (IC) design flow, rogue elements in the supply chain can pirate ICs, overbuild ICs, and insert hardware Trojans. EPIC locks the design by randomly inserting additional gates; only a correct key makes the design to produce correct outputs. We demonstrate that an attacker can decipher the locked netlist, in a time linear to the number of keys, by sensitizing the key-bits to the output. We then develop techniques to fix this vulnerability and make an attacker's effort truly exponential in the number of inserted keys. We introduce a new security metric and a method to deliver strong logic locking.",

keywords = "Design for trust, IP protection, hardware security, intellectual property (IP) piracy, logic encryption",

author = "Muhammad Yasin and Rajendran, {Jeyavijayan Jv} and Ozgur Sinanoglu and Ramesh Karri",

note = "Publisher Copyright: {\textcopyright} 1982-2012 IEEE.",

year = "2016",

month = sep,

doi = "10.1109/TCAD.2015.2511144",

language = "English (US)",

volume = "35",

pages = "1411--1424",

journal = "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems",

issn = "0278-0070",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "9",

}

TY - JOUR

T1 - On Improving the Security of Logic Locking

AU - Yasin, Muhammad

AU - Rajendran, Jeyavijayan Jv

AU - Sinanoglu, Ozgur

AU - Karri, Ramesh

PY - 2016/9

Y1 - 2016/9

N2 - Due to globalization of integrated circuit (IC) design flow, rogue elements in the supply chain can pirate ICs, overbuild ICs, and insert hardware Trojans. EPIC locks the design by randomly inserting additional gates; only a correct key makes the design to produce correct outputs. We demonstrate that an attacker can decipher the locked netlist, in a time linear to the number of keys, by sensitizing the key-bits to the output. We then develop techniques to fix this vulnerability and make an attacker's effort truly exponential in the number of inserted keys. We introduce a new security metric and a method to deliver strong logic locking.

AB - Due to globalization of integrated circuit (IC) design flow, rogue elements in the supply chain can pirate ICs, overbuild ICs, and insert hardware Trojans. EPIC locks the design by randomly inserting additional gates; only a correct key makes the design to produce correct outputs. We demonstrate that an attacker can decipher the locked netlist, in a time linear to the number of keys, by sensitizing the key-bits to the output. We then develop techniques to fix this vulnerability and make an attacker's effort truly exponential in the number of inserted keys. We introduce a new security metric and a method to deliver strong logic locking.

KW - Design for trust

KW - IP protection

KW - hardware security

KW - intellectual property (IP) piracy

KW - logic encryption

UR - http://www.scopus.com/inward/record.url?scp=84983801222&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84983801222&partnerID=8YFLogxK

U2 - 10.1109/TCAD.2015.2511144

DO - 10.1109/TCAD.2015.2511144

M3 - Article

AN - SCOPUS:84983801222

SN - 0278-0070

VL - 35

SP - 1411

EP - 1424

JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

IS - 9

M1 - 7362173

ER -

On Improving the Security of Logic Locking

Abstract

Keywords

ASJC Scopus subject areas

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