On physical limits and challenges of graphene nanoribbons as interconnects for all-spin logic

The semiconducting material silicon is at the heart of the current complementary metal-oxide-semiconductor (CMOS) technology, which today has developed into a $270-billion market [1]. Over the last four decades as the minimum feature size (MFS) on the microprocessor has shrunk from a few microns to tens of nanometers, the productivity of the silicon technology has roughly increased by a factor of billion [1]. Dr. G. Moore from Intel first pointed out this exponential growth in the semiconductor industry; his observation later became the celebrated Moore’s law. It is, indeed, Moore’s law that has driven the economics of the semiconductor industry by setting targets for research and development over the past few decades. However, as we move into an era of sub-10 nm technology nodes, it is natural to ask if Moore’s law will hold forever. One of the main limits of dimensional scaling is the power barrier of the CMOS technology. It is now well established that the fundamental limit of the energy dissipation of a single binary transition in a CMOS switch is κ_B T ln2, where κ_B is the Boltzmann constant, and T is the temperature of the system [2-4]. Using materials other than silicon to implement field-effect transistors (FETs) might provide one-time performance gains but will eventually be plagued by the same fundamental limits governing siliconbased FETs [5].