On the Correlation between Controller Faults and Instruction-Level Errors in Modern Microprocessors

Naghmeh Karimiy, Michail Maniatakos, Abhijit Jas, Yiorgos Makris

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We investigate the correlation between register transfer-level faults in the control logic of a modern microprocessor and their instruction-level impact on the execution flow of typical programs. Such information can prove immensely useful in accurately assessing and prioritizing faults with regards to their criticality, as well as commensurately allocating resources to enhance testability, diagnosability, manufacturability and reliability. To this end, we developed an extensive infrastructure which allows injection of stuck-at faults and transient errors of arbitrary starting point and duration, as well as cost-effective simulation and classification of their repercussions into various instruction-level error types. As a test vehicle for our study, we employ a superscalar, dynamically-scheduled, out-of-order, Alpha-like microprocessor, on which we execute SPEC2000 integer benchmarks. Extensive experimentation with faults injected in control logic modules of this microprocessor reveals interesting trends and results, corroborating the utility of this simulation infrastructure and motivating its further development and application to various tasks related to robust design.

Original languageEnglish (US)
Title of host publicationProceedings - International Test Conference 2008, ITC 2008
DOIs
StatePublished - 2008
EventInternational Test Conference 2008, ITC 2008 - Santa Clara, CA, United States
Duration: Oct 28 2008Oct 30 2008

Publication series

NameProceedings - International Test Conference
ISSN (Print)1089-3539

Other

OtherInternational Test Conference 2008, ITC 2008
CountryUnited States
CitySanta Clara, CA
Period10/28/0810/30/08

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Applied Mathematics

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