TY - GEN
T1 - Opportunities and pitfalls of multi-core scaling using hardware transaction memory
AU - Wang, Zhaoguo
AU - Qian, Hao
AU - Chen, Haibo
AU - Li, Jinyang
N1 - Copyright:
Copyright 2013 Elsevier B.V., All rights reserved.
PY - 2013
Y1 - 2013
N2 - Hardware transactional memory, which holds the promise to simplify and scale up multicore synchronization, has recently become available in main stream processors in the form of Intel's restricted transactional memory (RTM). Will RTM be a panacea for multicore scaling? This paper tries to shed some light on this question by studying the performance scalability of a concurrent skip list using competing synchronization techniques, including fine-grained locking, lock-free and RTM (using both Intel's RTM emulator and a real RTM machine). Our experience suggests that RTM indeed simplifies the implementation, however, a lot of care must be taken to get good performance. Specifically, to avoid excessive aborts due to RTM capacity miss or conflicts, programmers should move memory allocation/deallocation out of RTM region, tuning fallback functions, and use compiler optimization.
AB - Hardware transactional memory, which holds the promise to simplify and scale up multicore synchronization, has recently become available in main stream processors in the form of Intel's restricted transactional memory (RTM). Will RTM be a panacea for multicore scaling? This paper tries to shed some light on this question by studying the performance scalability of a concurrent skip list using competing synchronization techniques, including fine-grained locking, lock-free and RTM (using both Intel's RTM emulator and a real RTM machine). Our experience suggests that RTM indeed simplifies the implementation, however, a lot of care must be taken to get good performance. Specifically, to avoid excessive aborts due to RTM capacity miss or conflicts, programmers should move memory allocation/deallocation out of RTM region, tuning fallback functions, and use compiler optimization.
UR - http://www.scopus.com/inward/record.url?scp=84883112612&partnerID=8YFLogxK
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U2 - 10.1145/2500727.2500745
DO - 10.1145/2500727.2500745
M3 - Conference contribution
AN - SCOPUS:84883112612
SN - 9781450323161
T3 - Proceedings of the 4th Asia-Pacific Workshop on Systems, APSys 2013
BT - Proceedings of the 4th Asia-Pacific Workshop on Systems, APSys 2013
T2 - 4th Asia-Pacific Workshop on Systems, APSys 2013
Y2 - 29 July 2013 through 30 July 2013
ER -