TY - GEN
T1 - Optimised predecessor data structures for internal memory
AU - Rahman, Naila
AU - Cole, Richard
AU - Raman, Rajeev
PY - 2001
Y1 - 2001
N2 - We demonstrate the importance of reducing misses in the translation-lookaside buffer (TLB) for obtaining good performance on modern computer architectures. We focus on data structures for the dynamic predecessor problem: to maintain a set S of keys from a totally ordered universe under insertions, deletions and predecessor queries. We give two general techniques for simultaneously reducing cache and TLB misses: simulating 3-level hierarchical memory algorithms and cache-oblivious algorithms. We give preliminary experimental results which demonstrate that data structures based on these ideas outperform data structures which are based on minimising cache misses alone, namely B-tree variants.
AB - We demonstrate the importance of reducing misses in the translation-lookaside buffer (TLB) for obtaining good performance on modern computer architectures. We focus on data structures for the dynamic predecessor problem: to maintain a set S of keys from a totally ordered universe under insertions, deletions and predecessor queries. We give two general techniques for simultaneously reducing cache and TLB misses: simulating 3-level hierarchical memory algorithms and cache-oblivious algorithms. We give preliminary experimental results which demonstrate that data structures based on these ideas outperform data structures which are based on minimising cache misses alone, namely B-tree variants.
UR - http://www.scopus.com/inward/record.url?scp=78650747954&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=78650747954&partnerID=8YFLogxK
U2 - 10.1007/3-540-44688-5_6
DO - 10.1007/3-540-44688-5_6
M3 - Conference contribution
AN - SCOPUS:78650747954
SN - 3540425004
SN - 9783540425007
T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
SP - 67
EP - 78
BT - Algorithm Engineering - 5th International Workshop, WAE 2001, Proceedings
T2 - 5th International Workshop on Algorithm Engineering, WAE 2001
Y2 - 28 August 2010 through 31 August 2010
ER -