Optimization of the V_T-control method for low-power ultra-thin double-gate SOI logic circuits

Application of the V_T-control method is studied in ultra-thin double-gate (DG) SOI inverter, as the simplest building block of SOI logic circuits. Two control voltages, V_CN and V_CP, are applied to the back-gates of the n- and p-type transistors, respectively, to reduce the leakage current when the inverter is in the idle mode. Simulations with DESSIS disclose that both control voltages may be set at an optimum value for a given circuit activity, leading to the lowest possible gate power-delay product. Simulations have been performed for 10 nm gate-length technology at the end of the ITRS roadmap. These results indicate that the optimized V _T-control method is a promising way for realizing low-power SOI logic circuits. Furthermore, the scalability of this technique is verified by extending the simulations to other generations of the ITRS roadmap.