TY - GEN
T1 - Optimization of the VT-control method for low-power ultra-thin double-gate SOI logic circuits
AU - Shahrjerdi, Davood
AU - Hekmatshoar, Bahman
AU - Afzali-Kusha, Ali
AU - Khakifirooz, Ali
N1 - Copyright:
Copyright 2020 Elsevier B.V., All rights reserved.
PY - 2004
Y1 - 2004
N2 - Application of the VT-control method is studied in ultrathin double-gate (DG) SOI inverter, as the simplest building block of SOI logic circuits. Two control voltages, VCN and VCP, are applied to the back-gates of the n-type and p-type transistors, respectively, to reduce the leakage current when the inverter is in the idle mode. Simulations with DESSIS disclose that both control voltages may be set at an optimum value for a given circuit activity, leading to the lowest possible gate power-delay product. Simulations have been performed for 10 nm gate-length technology at the end of the ITRS roadmap. These results indicate that the optimized V T-control method is a promising way for realizing low-power SOI logic circuits.
AB - Application of the VT-control method is studied in ultrathin double-gate (DG) SOI inverter, as the simplest building block of SOI logic circuits. Two control voltages, VCN and VCP, are applied to the back-gates of the n-type and p-type transistors, respectively, to reduce the leakage current when the inverter is in the idle mode. Simulations with DESSIS disclose that both control voltages may be set at an optimum value for a given circuit activity, leading to the lowest possible gate power-delay product. Simulations have been performed for 10 nm gate-length technology at the end of the ITRS roadmap. These results indicate that the optimized V T-control method is a promising way for realizing low-power SOI logic circuits.
KW - Double-Gate SOI
KW - Dynamic Threshold Voltage
KW - Low-Power
UR - http://www.scopus.com/inward/record.url?scp=2942687161&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=2942687161&partnerID=8YFLogxK
U2 - 10.1145/988952.989009
DO - 10.1145/988952.989009
M3 - Conference contribution
AN - SCOPUS:2942687161
SN - 1581138539
SN - 9781581138535
T3 - Proceedings of the ACM Great Lakes Symposium on VLSI
SP - 236
EP - 239
BT - Proceedings of the 2004 ACM Great Lakes Symposium on VLSI, GLSVLSI 2004
PB - Association for Computing Machinery
T2 - Proceedings of the 2004 ACM Great lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era
Y2 - 26 April 2004 through 28 April 2004
ER -