Optimization of the VT-control method for low-power ultra-thin double-gate SOI logic circuits

Davood Shahrjerdi; Bahman Hekmatshoar; Ali Afzali-Kusha; Ali Khakifirooz

doi:10.1145/988952.989009

Optimization of the V_T-control method for low-power ultra-thin double-gate SOI logic circuits

Davood Shahrjerdi, Bahman Hekmatshoar, Ali Afzali-Kusha, Ali Khakifirooz

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Application of the V_T-control method is studied in ultrathin double-gate (DG) SOI inverter, as the simplest building block of SOI logic circuits. Two control voltages, V_CN and V_CP, are applied to the back-gates of the n-type and p-type transistors, respectively, to reduce the leakage current when the inverter is in the idle mode. Simulations with DESSIS disclose that both control voltages may be set at an optimum value for a given circuit activity, leading to the lowest possible gate power-delay product. Simulations have been performed for 10 nm gate-length technology at the end of the ITRS roadmap. These results indicate that the optimized V _T-control method is a promising way for realizing low-power SOI logic circuits.

Original language	English (US)
Title of host publication	Proceedings of the 2004 ACM Great Lakes Symposium on VLSI, GLSVLSI 2004
Subtitle of host publication	VLSI in the Nanometer Era
Publisher	Association for Computing Machinery
Pages	236-239
Number of pages	4
ISBN (Print)	1581138539, 9781581138535
DOIs	https://doi.org/10.1145/988952.989009
State	Published - 2004
Event	Proceedings of the 2004 ACM Great lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era - Boston, MA, United States Duration: Apr 26 2004 → Apr 28 2004

Publication series

Name	Proceedings of the ACM Great Lakes Symposium on VLSI

Other

Other	Proceedings of the 2004 ACM Great lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era
Country/Territory	United States
City	Boston, MA
Period	4/26/04 → 4/28/04

Keywords

Double-Gate SOI
Dynamic Threshold Voltage
Low-Power

ASJC Scopus subject areas

Engineering(all)

Access to Document

10.1145/988952.989009

Cite this

Shahrjerdi, D., Hekmatshoar, B., Afzali-Kusha, A., & Khakifirooz, A. (2004). Optimization of the V_T-control method for low-power ultra-thin double-gate SOI logic circuits. In Proceedings of the 2004 ACM Great Lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era (pp. 236-239). (Proceedings of the ACM Great Lakes Symposium on VLSI). Association for Computing Machinery. https://doi.org/10.1145/988952.989009

Optimization of the V_T-control method for low-power ultra-thin double-gate SOI logic circuits. / Shahrjerdi, Davood; Hekmatshoar, Bahman; Afzali-Kusha, Ali et al.

Proceedings of the 2004 ACM Great Lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era. Association for Computing Machinery, 2004. p. 236-239 (Proceedings of the ACM Great Lakes Symposium on VLSI).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Shahrjerdi, D, Hekmatshoar, B, Afzali-Kusha, A & Khakifirooz, A 2004, Optimization of the V_T-control method for low-power ultra-thin double-gate SOI logic circuits. in Proceedings of the 2004 ACM Great Lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era. Proceedings of the ACM Great Lakes Symposium on VLSI, Association for Computing Machinery, pp. 236-239, Proceedings of the 2004 ACM Great lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era, Boston, MA, United States, 4/26/04. https://doi.org/10.1145/988952.989009

Shahrjerdi D, Hekmatshoar B, Afzali-Kusha A, Khakifirooz A. Optimization of the V_T-control method for low-power ultra-thin double-gate SOI logic circuits. In Proceedings of the 2004 ACM Great Lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era. Association for Computing Machinery. 2004. p. 236-239. (Proceedings of the ACM Great Lakes Symposium on VLSI). doi: 10.1145/988952.989009

Shahrjerdi, Davood ; Hekmatshoar, Bahman ; Afzali-Kusha, Ali et al. / Optimization of the V_T-control method for low-power ultra-thin double-gate SOI logic circuits. Proceedings of the 2004 ACM Great Lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era. Association for Computing Machinery, 2004. pp. 236-239 (Proceedings of the ACM Great Lakes Symposium on VLSI).

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abstract = "Application of the VT-control method is studied in ultrathin double-gate (DG) SOI inverter, as the simplest building block of SOI logic circuits. Two control voltages, VCN and VCP, are applied to the back-gates of the n-type and p-type transistors, respectively, to reduce the leakage current when the inverter is in the idle mode. Simulations with DESSIS disclose that both control voltages may be set at an optimum value for a given circuit activity, leading to the lowest possible gate power-delay product. Simulations have been performed for 10 nm gate-length technology at the end of the ITRS roadmap. These results indicate that the optimized V T-control method is a promising way for realizing low-power SOI logic circuits.",

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