Optimizing Constrained-Modulus Barrett Multiplier for Power and Flexibility

Deepraj Soni, Mohammed Nabeel, Ramesh Karri, Michail Maniatakos

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Fully Homomorphic Encryption (FHE) promises data protection by computing on encrypted data, but demands resource-intensive computation. FHE hardware accelerators, which improve FHE scheme performance with densely packed computing units, could potentially damage the chip with excessive heat dissipation because of high power consumption. Therefore, it is necessary to reduce the power consumption of the accelerator and its most critical module, i.e., modular multiplier. In this work, we extend the idea of allowing a specific form of modulus to achieve a low-power Barrett modular multiplier (BM). BM with constraint width can reduce power consumption by 15% and area by 20%. We propose an approximation for the number of moduli available with the discussed constraints on the modulus.

Original languageEnglish (US)
Title of host publication2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration, VLSI-SoC 2023
PublisherIEEE Computer Society
ISBN (Electronic)9798350325997
DOIs
StatePublished - 2023
Event31st IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2023 - Dubai, United Arab Emirates
Duration: Oct 16 2023Oct 18 2023

Publication series

NameIEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
ISSN (Print)2324-8432
ISSN (Electronic)2324-8440

Conference

Conference31st IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2023
Country/TerritoryUnited Arab Emirates
CityDubai
Period10/16/2310/18/23

Keywords

  • ASIC Design
  • Barrett Reduction
  • Fully Homomorphic Encryption
  • Low-power design
  • Modular Multiplier

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software
  • Electrical and Electronic Engineering

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