TY - GEN
T1 - Optimizing Constrained-Modulus Barrett Multiplier for Power and Flexibility
AU - Soni, Deepraj
AU - Nabeel, Mohammed
AU - Karri, Ramesh
AU - Maniatakos, Michail
N1 - Publisher Copyright:
© 2023 IEEE.
PY - 2023
Y1 - 2023
N2 - Fully Homomorphic Encryption (FHE) promises data protection by computing on encrypted data, but demands resource-intensive computation. FHE hardware accelerators, which improve FHE scheme performance with densely packed computing units, could potentially damage the chip with excessive heat dissipation because of high power consumption. Therefore, it is necessary to reduce the power consumption of the accelerator and its most critical module, i.e., modular multiplier. In this work, we extend the idea of allowing a specific form of modulus to achieve a low-power Barrett modular multiplier (BM). BM with constraint width can reduce power consumption by 15% and area by 20%. We propose an approximation for the number of moduli available with the discussed constraints on the modulus.
AB - Fully Homomorphic Encryption (FHE) promises data protection by computing on encrypted data, but demands resource-intensive computation. FHE hardware accelerators, which improve FHE scheme performance with densely packed computing units, could potentially damage the chip with excessive heat dissipation because of high power consumption. Therefore, it is necessary to reduce the power consumption of the accelerator and its most critical module, i.e., modular multiplier. In this work, we extend the idea of allowing a specific form of modulus to achieve a low-power Barrett modular multiplier (BM). BM with constraint width can reduce power consumption by 15% and area by 20%. We propose an approximation for the number of moduli available with the discussed constraints on the modulus.
KW - ASIC Design
KW - Barrett Reduction
KW - Fully Homomorphic Encryption
KW - Low-power design
KW - Modular Multiplier
UR - http://www.scopus.com/inward/record.url?scp=85179848000&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85179848000&partnerID=8YFLogxK
U2 - 10.1109/VLSI-SoC57769.2023.10321936
DO - 10.1109/VLSI-SoC57769.2023.10321936
M3 - Conference contribution
AN - SCOPUS:85179848000
T3 - IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
BT - 2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration, VLSI-SoC 2023
PB - IEEE Computer Society
T2 - 31st IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2023
Y2 - 16 October 2023 through 18 October 2023
ER -