Optimizing the Use of Behavioral Locking for High-Level Synthesis

Christian Pilato, Luca Collini, Luca Cassano, Donatella Sciuto, Siddharth Garg, Ramesh Karri

Research output: Contribution to journalArticlepeer-review


The globalization of the electronics supply chain requires effective methods to thwart reverse engineering and intellectual property (IP) theft. Logic locking is a promising solution, but there are many open concerns. First, even when applied at a higher level of abstraction, locking may result in significant overhead without improving the security metric. Second, optimizing a security metric is application-dependent and designers must evaluate and compare alternative solutions. We propose a metaframework to optimize the use of behavioral locking during the high-level synthesis (HLS) of IP cores. Our method operates on chip's specification (before HLS) and it is compatible with all HLS tools, complementing industrial EDA flows. Our metaframework supports different strategies to explore the design space and to select points to be locked automatically. We evaluated our method on the optimization of differential entropy, achieving better results than random or topological locking: 1) we always identify a valid solution that optimizes the security metric, while topological and random locking can generate unfeasible solutions; 2) we minimize the number of bits used for locking up to more than 90% (requiring smaller tamper-proof memories); and 3) we make better use of hardware resources since we obtain similar overheads but with higher security metric.

Original languageEnglish (US)
Pages (from-to)462-472
Number of pages11
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Issue number2
StatePublished - Feb 1 2023


  • Hardware security
  • high-level synthesis (HLS)
  • intellectual property (IP) protection
  • logic locking

ASJC Scopus subject areas

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering


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