TY - GEN
T1 - Packet transactions
T2 - 2016 ACM Conference on Special Interest Group on Data Communication, SIGCOMM 2016
AU - Sivaraman, Anirudh
AU - Cheung, Alvin
AU - Budiu, Mihai
AU - Kim, Changhoon
AU - Alizadeh, Mohammad
AU - Balakrishnan, Hari
AU - Varghese, George
AU - McKeown, Nick
AU - Licking, Steve
N1 - Publisher Copyright:
© 2016 Copyright held by the owner/author(s).
PY - 2016/8/22
Y1 - 2016/8/22
N2 - Many algorithms for congestion control, scheduling, network measurement, active queue management, and traffic engineering require custom processing of packets in the data plane of a network switch. To run at line rate, these dataplane algorithms must be implemented in hardware. With today's switch hardware, algorithms cannot be changed, nor new algorithms installed, after a switch has been built. This paper shows how to program data-plane algorithms in a high-level language and compile those programs into low-level microcode that can run on emerging programmable line-rate switching chips. The key challenge is that many data-plane algorithms create and modify algorithmic state. To achieve line-rate programmability for stateful algorithms, we introduce the notion of a packet transaction: a sequential packet-processing code block that is atomic and isolated from other such code blocks. We have developed this idea in Domino, a C-like imperative language to express data-plane algorithms. We show with many examples that Domino provides a convenient way to express sophisticated data-plane algorithms, and show that these algorithms can be run at line rate with modest estimated chip-area overhead.
AB - Many algorithms for congestion control, scheduling, network measurement, active queue management, and traffic engineering require custom processing of packets in the data plane of a network switch. To run at line rate, these dataplane algorithms must be implemented in hardware. With today's switch hardware, algorithms cannot be changed, nor new algorithms installed, after a switch has been built. This paper shows how to program data-plane algorithms in a high-level language and compile those programs into low-level microcode that can run on emerging programmable line-rate switching chips. The key challenge is that many data-plane algorithms create and modify algorithmic state. To achieve line-rate programmability for stateful algorithms, we introduce the notion of a packet transaction: a sequential packet-processing code block that is atomic and isolated from other such code blocks. We have developed this idea in Domino, a C-like imperative language to express data-plane algorithms. We show with many examples that Domino provides a convenient way to express sophisticated data-plane algorithms, and show that these algorithms can be run at line rate with modest estimated chip-area overhead.
KW - Programmable switches
KW - Stateful data-plane algorithms
UR - http://www.scopus.com/inward/record.url?scp=84986587169&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84986587169&partnerID=8YFLogxK
U2 - 10.1145/2934872.2934900
DO - 10.1145/2934872.2934900
M3 - Conference contribution
AN - SCOPUS:84986587169
T3 - SIGCOMM 2016 - Proceedings of the 2016 ACM Conference on Special Interest Group on Data Communication
SP - 15
EP - 28
BT - SIGCOMM 2016 - Proceedings of the 2016 ACM Conference on Special Interest Group on Data Communication
PB - Association for Computing Machinery, Inc
Y2 - 22 August 2016 through 26 August 2016
ER -