Memristors are employed by a wide variety of applications such as neural networks, memory and digital logic. However, the process variation effects of memristors may affect these applications. In this research, we consider the effect of process variations in the thickness of the oxide layer of memristors that are used in Memristor-based Threshold Logic (MTL) gates. As the effect of variations is less pronounced in high memristance values, a variation tolerant design without any degradation in speed is achieved by having a number of high memristance devices in parallel (redundancy factor). We propose an algorithm for the MTL gates to determine the number of memristors in parallel and the variation-minimal high memristance state. A power optimization algorithm is also proposed to map gates in a design using different libraries that have different performance characteristics. Finally, we present the power, delay performance and also the redundancy factor of memristors for various benchmark circuits.