Parity-based output compaction for core-based SOCs [logic testing]

O. Sinanoglu, A. Orailoglu

Research output: Chapter in Book/Report/Conference proceedingConference contribution


SOC test application time is strongly determined by the parallelism attained among core tests. Yet, test bandwidth allocation issues typically impose significant limitations on parallel testing of the cores. In this paper, we propose a response compaction methodology for reducing the required output bandwidth of cores, enabling increased parallelism among core tests and hence reducing overall SOC test time. The proposed methodology is based on judiciously partitioning test responses, with each response fragment being compacted individually. The signature corresponding to the response fragments consists of the parity information which is computed through a cost-effective on-chip space and time compaction mechanism. We show that the proposed technique not only delivers negligible aliasing for any (modeled or unmodeled) fault but that it also provides diagnostic and unknown response value handling capabilities.

Original languageEnglish (US)
Title of host publicationProceedings - 8th IEEE European Test Workshop, ETW 2003
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages6
ISBN (Electronic)0769519083
StatePublished - 2003
Event8th IEEE European Test Workshop, ETW 2003 - Maastricht, Netherlands
Duration: May 25 2003May 28 2003

Publication series

NameProceedings of the European Test Workshop
ISSN (Print)1530-1877
ISSN (Electronic)1558-1780


Other8th IEEE European Test Workshop, ETW 2003


  • Application software
  • Bandwidth
  • Channel allocation
  • Circuit faults
  • Circuit testing
  • Compaction
  • Computer science
  • Parallel processing
  • Test data compression
  • Transportation

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Industrial and Manufacturing Engineering
  • Software


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