Peak power reduction through dynamic partitioning of scan chains

Sobeeh Almukhaizim, Ozgur Sinanoglu

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Serial shift operations in scan-based testing impose elevated levels ofpower dissipation, endangering the reliability of the chip being tested. Scan chain partitioning techniques are quite effective in reducing test power, as the rippling in the clock network, in the scan chains, and in the combination logic is reduced altogether Partitioning approaches implemented in a static manner may fail to reduce peak power down to the desired level, however, depending on the transition distribution of the problematic pattern in the statically constructed scan chain partitions. In this paper, we propose a dynamic partitioning approach capable of adapting to the transition distribution of any test pattern, and thus of delivering near-perfect peak power reductions. Weformulate the scan chain partitioningproblem via Integer Linear Programming (ILP) and also propose an efficient greedy heuristic. The proposedpartitioning hardware allowsfor the partitioning reconfiguration on a per test pattern basis, enabling the dynamic partitioning. Significant peakpower reductionsare thus attained cost-effectively.

Original languageEnglish (US)
Title of host publicationProceedings - International Test Conference 2008, ITC 2008
StatePublished - 2008
EventInternational Test Conference 2008, ITC 2008 - Santa Clara, CA, United States
Duration: Oct 28 2008Oct 30 2008

Publication series

NameProceedings - International Test Conference
ISSN (Print)1089-3539


OtherInternational Test Conference 2008, ITC 2008
Country/TerritoryUnited States
CitySanta Clara, CA

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Applied Mathematics


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