Performance, energy-per-bit, and circuit size limits of post-CMOS logic circuits-modeling, analysis and comparison with CMOS logic

Shaloo Rakheja, Azad Naeemi

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Original language	English (US)
Title of host publication	IEEE International Interconnect Technology Conference (IITC), Dresden, Germany. May 8-12, 2011
State	Published - 2011

Cite this

@inproceedings{a2d533a30c9c4ff4b8741d729c2bec6d,

title = "Performance, energy-per-bit, and circuit size limits of post-CMOS logic circuits-modeling, analysis and comparison with CMOS logic",

author = "Shaloo Rakheja and Azad Naeemi",

year = "2011",

language = "English (US)",

booktitle = "IEEE International Interconnect Technology Conference (IITC), Dresden, Germany. May 8-12, 2011",

}