In this paper, performance models of different network-on-chip (NoC) topologies are developed by a) incorporating physical models of the interconnect structures, and b) specifying the microarchitecture of cores and on-chip routers at 15 nm technology node for a clock frequency of 4 GHz. By incorporating device and interconnect models, we implement a cross-layer design and optimization of the performance of NoC architectures. The performance modeling is carried out for mesh, torus, and flattened butterfly (FBFLY) NoC topologies by focusing on global copper (Cu/low-κ) and graphene nanoribbons (GNRs) as the interconnect infrastructure for inter-core communication. The findings show that mesh NoCs incorporated with Cu/low-κ or GNRs have the same latency metrics, while for torus and FBFLY NoCs, the high latency of GNR interconnects is prohibitive. Mesh, torus, and FBFLY topologies with GNRs as inter-core interconnects result in lower interconnect energy dissipation compared to Cu/low-κ interconnects. The worst-case delay for mesh NoCs is equally governed by the on-chip router delay and inter-core interconnects delay but for torus and FBFLY NoCs, delay form inter-core interconnects particularly limits their performance. Therefore, ignoring the interconnect latency in this analysis overestimates the NoC performance significantly. We also determine the optimal network size up to which networks on-chip (NoCs) with GNR interconnects give lower energy-delay product (EDP) when compared against Cu/low-κ interconnects. The results obtained in this paper are representative of on-die router implementations at 15 nm technology node, which can be used to predict the realistic performance of various NoC topologies.