Performance modeling for interconnects for conventional and emerging switches

Shaloo Rakheja, Vachan Kumar, Azad Naeemi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper quantifies the challenges, limits, and opportunities of interconnects for evolutionary and revolutionary semiconductor technologies of the future. Various exploratory devices and the delays associated with their transport mechanisms are quantified. Graphene is selected as the interconnect material of choice because of its excellent transport properties over the conventional Cu/low-K: interconnects currently serving as the communication medium in integrated circuits. Compact models that describe the transport properties in graphene (electron mean free path, mobility, spin relaxation) are presented. These compact models are used to (i) evaluate the performance and energy-per-bit of graphene interconnects in electrical and spintronic domains and (ii) compare these metrics against those of conventional electrical interconnects at the end of silicon roadmap technology node (minimum feature size of 7.5 nm).

Original languageEnglish (US)
Title of host publication2013 ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2013
PublisherAssociation for Computing Machinery
ISBN (Print)9781467361736
DOIs
StatePublished - 2013
Event2013 ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2013 - Austin, TX, United States
Duration: Jun 2 2013Jun 2 2013

Publication series

NameInternational Workshop on System Level Interconnect Prediction, SLIP

Other

Other2013 ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2013
CountryUnited States
CityAustin, TX
Period6/2/136/2/13

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Applied Mathematics

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