TY - GEN
T1 - Performance modeling for interconnects for conventional and emerging switches
AU - Rakheja, Shaloo
AU - Kumar, Vachan
AU - Naeemi, Azad
PY - 2013
Y1 - 2013
N2 - This paper quantifies the challenges, limits, and opportunities of interconnects for evolutionary and revolutionary semiconductor technologies of the future. Various exploratory devices and the delays associated with their transport mechanisms are quantified. Graphene is selected as the interconnect material of choice because of its excellent transport properties over the conventional Cu/low-K: interconnects currently serving as the communication medium in integrated circuits. Compact models that describe the transport properties in graphene (electron mean free path, mobility, spin relaxation) are presented. These compact models are used to (i) evaluate the performance and energy-per-bit of graphene interconnects in electrical and spintronic domains and (ii) compare these metrics against those of conventional electrical interconnects at the end of silicon roadmap technology node (minimum feature size of 7.5 nm).
AB - This paper quantifies the challenges, limits, and opportunities of interconnects for evolutionary and revolutionary semiconductor technologies of the future. Various exploratory devices and the delays associated with their transport mechanisms are quantified. Graphene is selected as the interconnect material of choice because of its excellent transport properties over the conventional Cu/low-K: interconnects currently serving as the communication medium in integrated circuits. Compact models that describe the transport properties in graphene (electron mean free path, mobility, spin relaxation) are presented. These compact models are used to (i) evaluate the performance and energy-per-bit of graphene interconnects in electrical and spintronic domains and (ii) compare these metrics against those of conventional electrical interconnects at the end of silicon roadmap technology node (minimum feature size of 7.5 nm).
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U2 - 10.1109/SLIP.2013.6681683
DO - 10.1109/SLIP.2013.6681683
M3 - Conference contribution
AN - SCOPUS:84893353567
SN - 9781467361736
T3 - International Workshop on System Level Interconnect Prediction, SLIP
BT - 2013 ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2013
PB - Association for Computing Machinery
T2 - 2013 ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2013
Y2 - 2 June 2013 through 2 June 2013
ER -