Performance modeling for interconnects for conventional and emerging switches

Shaloo Rakheja; Vachan Kumar; Azad Naeemi

doi:10.1109/SLIP.2013.6681683

Performance modeling for interconnects for conventional and emerging switches

Shaloo Rakheja, Vachan Kumar, Azad Naeemi

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper quantifies the challenges, limits, and opportunities of interconnects for evolutionary and revolutionary semiconductor technologies of the future. Various exploratory devices and the delays associated with their transport mechanisms are quantified. Graphene is selected as the interconnect material of choice because of its excellent transport properties over the conventional Cu/low-K: interconnects currently serving as the communication medium in integrated circuits. Compact models that describe the transport properties in graphene (electron mean free path, mobility, spin relaxation) are presented. These compact models are used to (i) evaluate the performance and energy-per-bit of graphene interconnects in electrical and spintronic domains and (ii) compare these metrics against those of conventional electrical interconnects at the end of silicon roadmap technology node (minimum feature size of 7.5 nm).

Original language	English (US)
Title of host publication	2013 ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2013
Publisher	Association for Computing Machinery
ISBN (Print)	9781467361736
DOIs	https://doi.org/10.1109/SLIP.2013.6681683
State	Published - 2013
Event	2013 ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2013 - Austin, TX, United States Duration: Jun 2 2013 → Jun 2 2013

Publication series

Name	International Workshop on System Level Interconnect Prediction, SLIP

Other

Other	2013 ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2013
Country/Territory	United States
City	Austin, TX
Period	6/2/13 → 6/2/13

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering
Computer Science Applications
Applied Mathematics

Access to Document

10.1109/SLIP.2013.6681683

Cite this

Rakheja, S., Kumar, V., & Naeemi, A. (2013). Performance modeling for interconnects for conventional and emerging switches. In 2013 ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2013 [6681683] (International Workshop on System Level Interconnect Prediction, SLIP). Association for Computing Machinery. https://doi.org/10.1109/SLIP.2013.6681683

Performance modeling for interconnects for conventional and emerging switches. / Rakheja, Shaloo; Kumar, Vachan; Naeemi, Azad.

2013 ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2013. Association for Computing Machinery, 2013. 6681683 (International Workshop on System Level Interconnect Prediction, SLIP).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Rakheja, S, Kumar, V & Naeemi, A 2013, Performance modeling for interconnects for conventional and emerging switches. in 2013 ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2013., 6681683, International Workshop on System Level Interconnect Prediction, SLIP, Association for Computing Machinery, 2013 ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2013, Austin, TX, United States, 6/2/13. https://doi.org/10.1109/SLIP.2013.6681683

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abstract = "This paper quantifies the challenges, limits, and opportunities of interconnects for evolutionary and revolutionary semiconductor technologies of the future. Various exploratory devices and the delays associated with their transport mechanisms are quantified. Graphene is selected as the interconnect material of choice because of its excellent transport properties over the conventional Cu/low-K: interconnects currently serving as the communication medium in integrated circuits. Compact models that describe the transport properties in graphene (electron mean free path, mobility, spin relaxation) are presented. These compact models are used to (i) evaluate the performance and energy-per-bit of graphene interconnects in electrical and spintronic domains and (ii) compare these metrics against those of conventional electrical interconnects at the end of silicon roadmap technology node (minimum feature size of 7.5 nm).",

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Performance modeling for interconnects for conventional and emerging switches

Abstract

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ASJC Scopus subject areas

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