Phantom redundancy: A high-level synthesis approach for manufacturability

Balakrishnan Iyer; Ramesh Karri; Israel Koren

Phantom redundancy: A high-level synthesis approach for manufacturability

Balakrishnan Iyer, Ramesh Karri, Israel Koren

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Phantom redundancy, an area-efficient technique for fabrication-time reconfigurability is presented. Phantom redundancy adds extra interconnect so as to render the resulting microarchitecture reconfigurable in the presence of any (single) functional unit failure. The proposed technique yields partially good chips in addition to perfect chips. A genetic algorithm is used to incorporate phantom redundancy constraints into microarchitecture synthesis. The algorithm minimizes the performance degradation due to any faulty functional unit of the resulting microarchitecture. The effectiveness of the technique is illustrated on benchmark examples.

Original language	English (US)
Title of host publication	IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
Editors	Anon
Publisher	IEEE
Pages	658-661
Number of pages	4
State	Published - 1995
Event	Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design - San Jose, CA, USA Duration: Nov 5 1995 → Nov 9 1995

Other

Other	Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design
City	San Jose, CA, USA
Period	11/5/95 → 11/9/95

ASJC Scopus subject areas

Software

Cite this

@inproceedings{7f85c7a702384953bb5ad6646fdbfbcd,

title = "Phantom redundancy: A high-level synthesis approach for manufacturability",

abstract = "Phantom redundancy, an area-efficient technique for fabrication-time reconfigurability is presented. Phantom redundancy adds extra interconnect so as to render the resulting microarchitecture reconfigurable in the presence of any (single) functional unit failure. The proposed technique yields partially good chips in addition to perfect chips. A genetic algorithm is used to incorporate phantom redundancy constraints into microarchitecture synthesis. The algorithm minimizes the performance degradation due to any faulty functional unit of the resulting microarchitecture. The effectiveness of the technique is illustrated on benchmark examples.",

author = "Balakrishnan Iyer and Ramesh Karri and Israel Koren",

year = "1995",

language = "English (US)",

pages = "658--661",

editor = "Anon",

booktitle = "IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers",

publisher = "IEEE",

note = "Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design ; Conference date: 05-11-1995 Through 09-11-1995",

}

TY - GEN

T1 - Phantom redundancy

T2 - Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design

AU - Iyer, Balakrishnan

AU - Karri, Ramesh

AU - Koren, Israel

PY - 1995

Y1 - 1995

N2 - Phantom redundancy, an area-efficient technique for fabrication-time reconfigurability is presented. Phantom redundancy adds extra interconnect so as to render the resulting microarchitecture reconfigurable in the presence of any (single) functional unit failure. The proposed technique yields partially good chips in addition to perfect chips. A genetic algorithm is used to incorporate phantom redundancy constraints into microarchitecture synthesis. The algorithm minimizes the performance degradation due to any faulty functional unit of the resulting microarchitecture. The effectiveness of the technique is illustrated on benchmark examples.

AB - Phantom redundancy, an area-efficient technique for fabrication-time reconfigurability is presented. Phantom redundancy adds extra interconnect so as to render the resulting microarchitecture reconfigurable in the presence of any (single) functional unit failure. The proposed technique yields partially good chips in addition to perfect chips. A genetic algorithm is used to incorporate phantom redundancy constraints into microarchitecture synthesis. The algorithm minimizes the performance degradation due to any faulty functional unit of the resulting microarchitecture. The effectiveness of the technique is illustrated on benchmark examples.

UR - http://www.scopus.com/inward/record.url?scp=0029492718&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0029492718&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0029492718

SP - 658

EP - 661

BT - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

A2 - Anon, null

PB - IEEE

Y2 - 5 November 1995 through 9 November 1995

ER -

Phantom redundancy: A high-level synthesis approach for manufacturability

Abstract

Other

ASJC Scopus subject areas

Other files and links

Fingerprint

Cite this