Abstract
Phantom redundancy, an area-efficient technique for fabrication-time reconfigurability is presented. Phantom redundancy adds extra interconnect so as to render the resulting microarchitecture reconfigurable in the presence of any (single) functional unit failure. The proposed technique yields partially good chips in addition to perfect chips. A genetic algorithm is used to incorporate phantom redundancy constraints into microarchitecture synthesis. The algorithm minimizes the performance degradation due to any faulty functional unit of the resulting microarchitecture. The effectiveness of the technique is illustrated on benchmark examples.
| Original language | English (US) |
|---|---|
| Title of host publication | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers |
| Editors | Anon |
| Publisher | IEEE |
| Pages | 658-661 |
| Number of pages | 4 |
| State | Published - 1995 |
| Event | Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design - San Jose, CA, USA Duration: Nov 5 1995 → Nov 9 1995 |
Other
| Other | Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design |
|---|---|
| City | San Jose, CA, USA |
| Period | 11/5/95 → 11/9/95 |
ASJC Scopus subject areas
- Software
Fingerprint Dive into the research topics of 'Phantom redundancy: A high-level synthesis approach for manufacturability'. Together they form a unique fingerprint.
Cite this
Iyer, B., Karri, R., & Koren, I. (1995). Phantom redundancy: A high-level synthesis approach for manufacturability. In Anon (Ed.), IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers (pp. 658-661). IEEE.