Phantom redundancy: A high-level synthesis approach for manufacturability

Balakrishnan Iyer, Ramesh Karri, Israel Koren

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Phantom redundancy, an area-efficient technique for fabrication-time reconfigurability is presented. Phantom redundancy adds extra interconnect so as to render the resulting microarchitecture reconfigurable in the presence of any (single) functional unit failure. The proposed technique yields partially good chips in addition to perfect chips. A genetic algorithm is used to incorporate phantom redundancy constraints into microarchitecture synthesis. The algorithm minimizes the performance degradation due to any faulty functional unit of the resulting microarchitecture. The effectiveness of the technique is illustrated on benchmark examples.

Original languageEnglish (US)
Title of host publicationIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
Editors Anon
PublisherIEEE
Pages658-661
Number of pages4
StatePublished - 1995
EventProceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design - San Jose, CA, USA
Duration: Nov 5 1995Nov 9 1995

Other

OtherProceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design
CitySan Jose, CA, USA
Period11/5/9511/9/95

ASJC Scopus subject areas

  • Software

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  • Cite this

    Iyer, B., Karri, R., & Koren, I. (1995). Phantom redundancy: A high-level synthesis approach for manufacturability. In Anon (Ed.), IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers (pp. 658-661). IEEE.