Phantom redundancy: A register transfer level technique for gracefully degradable data path synthesis

Ramesh Karri, Balakrishnan Iyer, Israel Koren

Research output: Contribution to journalArticle

Abstract

In this paper, the authors present an area-efficient register transfer level technique for gracefully degradable data path synthesis called phantom redundancy. In contrast to spare-based approaches, phantom redundancy is a recovery technique that does not use any standby spares. Phantom redundancy uses extra interconnect to make the resulting data path reconfigurable in the presence of any (single)functional unit failure. When phantom redundancy is combined with a concurrent error detection technique, error detection followed by reconfiguration is automatic. The authors developed a register transfer level synthesis algorithm that incorporates phantom redundancy constraints. There is a tight interdependence between reconfiguration of a (faulty) data path and scheduling and operation-to-operator binding tasks during register transfer level synthesis. They developed a genetic algorithm.based register transfer level synthesis approach to incorporate phantom redundancy constraints. The algorithm minimizes the performance degradation of the synthesized data path in the presence of any single faulty functional unit. The effectiveness of the technique and the algorithm are illustrated using high-level synthesis benchmarks.

Original languageEnglish (US)
Pages (from-to)877-888
Number of pages12
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume21
Issue number8
DOIs
StatePublished - Aug 2002

Keywords

  • Data path synthesis
  • Graceful degradation
  • Reconfigurable data paths
  • Register transfer level
  • VLSI testing

ASJC Scopus subject areas

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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