TY - GEN
T1 - Physical limitations on delay and energy dissipation of interconnects for post-CMOS devices
AU - Rakheja, Shaloo
AU - Naeemi, Azad
AU - Meindl, James D.
PY - 2010
Y1 - 2010
N2 - In order to maintain the historical scaling of computational power in information processing beyond the 2020 technology node, switches that are based on state variables other than electron charge are currently being investigated. Examples of alternate state variables include the electron spin, pseudo-spin in graphene, and excitons. This paper discusses different communication mechanisms for on-chip local interconnects for post-CMOS devices. Models for delay and energy dissipation for novel interconnects are obtained, and a comparison is provided with their CMOS counterpart. It is shown that novel interconnects can potentially consume less energy per bit as compared to the CMOS interconnects. However, they pose significant delay penalty. The paper highlights some of the major implications of the novel interconnects on the post-CMOS circuits.
AB - In order to maintain the historical scaling of computational power in information processing beyond the 2020 technology node, switches that are based on state variables other than electron charge are currently being investigated. Examples of alternate state variables include the electron spin, pseudo-spin in graphene, and excitons. This paper discusses different communication mechanisms for on-chip local interconnects for post-CMOS devices. Models for delay and energy dissipation for novel interconnects are obtained, and a comparison is provided with their CMOS counterpart. It is shown that novel interconnects can potentially consume less energy per bit as compared to the CMOS interconnects. However, they pose significant delay penalty. The paper highlights some of the major implications of the novel interconnects on the post-CMOS circuits.
UR - http://www.scopus.com/inward/record.url?scp=77955596315&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=77955596315&partnerID=8YFLogxK
U2 - 10.1109/IITC.2010.5510448
DO - 10.1109/IITC.2010.5510448
M3 - Conference contribution
AN - SCOPUS:77955596315
SN - 9781424476763
T3 - 2010 IEEE International Interconnect Technology Conference, IITC 2010
BT - 2010 IEEE International Interconnect Technology Conference, IITC 2010
T2 - 2010 IEEE International Interconnect Technology Conference, IITC 2010
Y2 - 6 June 2010 through 9 June 2010
ER -