Pipeline data path synthesis of fault - Tolerant microarchitectures

Microarchitectural implementation of a real-time signal processing algorithm for mission-critical applications (such as sensors on spacecrafts) is characterized by two unique requirements: real-time processing of a steady stream of input signals, which requires a high-performance implementation such as pipelining and reliable operation over the mission lifetime, which mandates support for faulttolerance. In this paper, we relate high-performance and fanlttolerance constraints to chip area, and present a methodology for synthesizing area-efficient microarchitectures satisfying these requirements. High-performance is achieved via pipelining, while desired fault-tolerance is realized using hardware redundancy. The framework has been used to synthesize high-performance and fault-tolerant microarchitectures for a variety of signal processing algorithms. Additionally, the framework has been used to explore design trade-offs between high-performance and high-reliability microarchitectures, subject to a maximum area constraint.