Pipeline data path synthesis of fault - Tolerant microarchitectures

Ramesh Karri, Alex Orailoglu

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Microarchitectural implementation of a real-time signal processing algorithm for mission-critical applications (such as sensors on spacecrafts) is characterized by two unique requirements: real-time processing of a steady stream of input signals, which requires a high-performance implementation such as pipelining and reliable operation over the mission lifetime, which mandates support for faulttolerance. In this paper, we relate high-performance and fanlttolerance constraints to chip area, and present a methodology for synthesizing area-efficient microarchitectures satisfying these requirements. High-performance is achieved via pipelining, while desired fault-tolerance is realized using hardware redundancy. The framework has been used to synthesize high-performance and fault-tolerant microarchitectures for a variety of signal processing algorithms. Additionally, the framework has been used to explore design trade-offs between high-performance and high-reliability microarchitectures, subject to a maximum area constraint.

Original languageEnglish (US)
Title of host publication1992 Proceedings of the 35th Midwest Symposium on Circuits and Systems
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages4
ISBN (Electronic)0780305108
StatePublished - 1992
Event35th Midwest Symposium on Circuits and Systems, MWSCAS 1992 - Washington, United States
Duration: Aug 9 1992Aug 12 1992

Publication series

NameMidwest Symposium on Circuits and Systems
ISSN (Print)1548-3746


Conference35th Midwest Symposium on Circuits and Systems, MWSCAS 1992
Country/TerritoryUnited States

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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