Attaining parallelism among core tests is of crucial importance to the reduction of SOC test costs. In this paper, we propose an SOC test methodology that enhances SOC test application throughput with no increase in test pin requirements. In the proposed methodology, the test vector of a core is formed in its scan chain by transforming the response of the preceding core; logic gates inserted between the core scan cells transform the response of the preceding core into the core test vector. The consequent core tests can be thought of as being pipelined, thus reducing the time spent for the delivery of the test vectors into the scan cells of the cores being tested in parallel, and hence increasing the throughput of SOC test application. The proposed algorithmic framework identifies the cost-effective hardware that maps the responses of the preceding core onto a maximal number of core test vectors through the utilization of efficient test vector and scan cell reordering heuristics; the impact of these techniques is modeled, enabling their utilization along with the aforementioned transformation techniques. We furthermore investigate various scan chain configuration techniques to enhance the pipeline efficiency, thus minimizing the pipeline period and the SOC test time. The efficacy of the proposed methodology translates into enhanced parallelism in testing SOC cores.