Post-SAT 3: Stripped-Functionality Logic Locking

Muhammad Yasin, Jeyavijayan (Jv) Rajendran, Ozgur Sinanoglu

Research output: Chapter in Book/Report/Conference proceedingChapter

Abstract

This chapter presents stripped-functionality logic locking (SFLL), a technique that provides provable security against SAT, removal, and approximate attacks. SFLL hides part of the design functionality in the form of compactly represented input patterns, rendering the on-chip circuit different from the original circuit. Only upon applying the correct key(s) to the restore circuit, the original functionality of the circuit is restored. This chapter presents SFLL, a logic locking technique that offers provable security guarantees against various classes of logic locking attacks. The underlying principle of logic locking is to implement a modified circuit on-chip; the difference in functionality is quantified in terms of the number of protected input patterns, which also dictates the protection achieved against various attacks. Only upon application of the correct key to a separately added restore circuit, the original functionality is restored. Section 9.1 explains the motivation behind SFLL and the basic concepts associated with SFLL. Section 9.2 introduces a special case of SFLL, referred to as SFLL-HD0, which protects only one pattern. Section 9.3 elaborates on the operation of the more general SFLL-HD scheme. Section 9.4 presents SFLL-flex that allows a designer to specify the functionality-to-be-protected.

Original languageEnglish (US)
Title of host publicationAnalog Circuits and Signal Processing
PublisherSpringer
Pages103-118
Number of pages16
DOIs
StatePublished - 2020

Publication series

NameAnalog Circuits and Signal Processing
ISSN (Print)1872-082X
ISSN (Electronic)2197-1854

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Information Systems
  • Signal Processing

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