Power, area, speed, and security (PASS) trade-offs of NIST PQC signature candidates using a C to ASIC design flow

Deepraj Soni; Mohammed Nabeel; Kanad Basu; Ramesh Karri

doi:10.1109/ICCD46524.2019.00054

Power, area, speed, and security (PASS) trade-offs of NIST PQC signature candidates using a C to ASIC design flow

Deepraj Soni, Mohammed Nabeel, Kanad Basu, Ramesh Karri

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

National Institute of Standards and Technology (NIST) is standardizing post-quantum cryptographic (PQC) algorithms. Most of the PQC algorithms are complex; rendering their hardware modeling, evaluation, and benchmarking challenging. We developed a High-Level Synthesis (HLS) → ASIC flow for fast evaluation of Power, Area, Speed, and Security (PASS) trade-offs of the NIST round 2 PQC algorithms using an industry-standard design flow. In this paper, we discuss this flow and the preliminary results on some of the PQC signature algorithms.

Original language	English (US)
Title of host publication	Proceedings - 2019 IEEE International Conference on Computer Design, ICCD 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	337-340
Number of pages	4
ISBN (Electronic)	9781538666487
DOIs	https://doi.org/10.1109/ICCD46524.2019.00054
State	Published - Nov 2019
Event	37th IEEE International Conference on Computer Design, ICCD 2019 - Abu Dhabi, United Arab Emirates Duration: Nov 17 2019 → Nov 20 2019

Publication series

Name	Proceedings - 2019 IEEE International Conference on Computer Design, ICCD 2019

Conference

Conference	37th IEEE International Conference on Computer Design, ICCD 2019
Country/Territory	United Arab Emirates
City	Abu Dhabi
Period	11/17/19 → 11/20/19

Keywords

Hardware implementation PQC
Hardware implementation of PQC
PQC algorithm
Signature scheme hardware implementation

ASJC Scopus subject areas

Information Systems and Management
Computer Networks and Communications
Control and Optimization
Hardware and Architecture

Access to Document

10.1109/ICCD46524.2019.00054

Cite this

Soni, D., Nabeel, M., Basu, K., & Karri, R. (2019). Power, area, speed, and security (PASS) trade-offs of NIST PQC signature candidates using a C to ASIC design flow. In Proceedings - 2019 IEEE International Conference on Computer Design, ICCD 2019 (pp. 337-340). Article 8988781 (Proceedings - 2019 IEEE International Conference on Computer Design, ICCD 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICCD46524.2019.00054

Power, area, speed, and security (PASS) trade-offs of NIST PQC signature candidates using a C to ASIC design flow. / Soni, Deepraj; Nabeel, Mohammed; Basu, Kanad et al.
Proceedings - 2019 IEEE International Conference on Computer Design, ICCD 2019. Institute of Electrical and Electronics Engineers Inc., 2019. p. 337-340 8988781 (Proceedings - 2019 IEEE International Conference on Computer Design, ICCD 2019).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Soni, D, Nabeel, M, Basu, K & Karri, R 2019, Power, area, speed, and security (PASS) trade-offs of NIST PQC signature candidates using a C to ASIC design flow. in Proceedings - 2019 IEEE International Conference on Computer Design, ICCD 2019., 8988781, Proceedings - 2019 IEEE International Conference on Computer Design, ICCD 2019, Institute of Electrical and Electronics Engineers Inc., pp. 337-340, 37th IEEE International Conference on Computer Design, ICCD 2019, Abu Dhabi, United Arab Emirates, 11/17/19. https://doi.org/10.1109/ICCD46524.2019.00054

Soni D, Nabeel M, Basu K, Karri R. Power, area, speed, and security (PASS) trade-offs of NIST PQC signature candidates using a C to ASIC design flow. In Proceedings - 2019 IEEE International Conference on Computer Design, ICCD 2019. Institute of Electrical and Electronics Engineers Inc. 2019. p. 337-340. 8988781. (Proceedings - 2019 IEEE International Conference on Computer Design, ICCD 2019). doi: 10.1109/ICCD46524.2019.00054

Soni, Deepraj ; Nabeel, Mohammed ; Basu, Kanad et al. / Power, area, speed, and security (PASS) trade-offs of NIST PQC signature candidates using a C to ASIC design flow. Proceedings - 2019 IEEE International Conference on Computer Design, ICCD 2019. Institute of Electrical and Electronics Engineers Inc., 2019. pp. 337-340 (Proceedings - 2019 IEEE International Conference on Computer Design, ICCD 2019).

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title = "Power, area, speed, and security (PASS) trade-offs of NIST PQC signature candidates using a C to ASIC design flow",

abstract = "National Institute of Standards and Technology (NIST) is standardizing post-quantum cryptographic (PQC) algorithms. Most of the PQC algorithms are complex; rendering their hardware modeling, evaluation, and benchmarking challenging. We developed a High-Level Synthesis (HLS) → ASIC flow for fast evaluation of Power, Area, Speed, and Security (PASS) trade-offs of the NIST round 2 PQC algorithms using an industry-standard design flow. In this paper, we discuss this flow and the preliminary results on some of the PQC signature algorithms.",

keywords = "Hardware implementation PQC, Hardware implementation of PQC, PQC algorithm, Signature scheme hardware implementation",

author = "Deepraj Soni and Mohammed Nabeel and Kanad Basu and Ramesh Karri",

note = "Funding Information: This work supported partly by NSF award 1526405 and CCS-AD. Publisher Copyright: {\textcopyright} 2019 IEEE.; 37th IEEE International Conference on Computer Design, ICCD 2019 ; Conference date: 17-11-2019 Through 20-11-2019",

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Power, area, speed, and security (PASS) trade-offs of NIST PQC signature candidates using a C to ASIC design flow

Abstract

Publication series

Conference

Keywords

ASJC Scopus subject areas

Access to Document

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