Power, area, speed, and security (PASS) trade-offs of NIST PQC signature candidates using a C to ASIC design flow

Deepraj Soni, Mohammed Nabeel, Kanad Basu, Ramesh Karri

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

National Institute of Standards and Technology (NIST) is standardizing post-quantum cryptographic (PQC) algorithms. Most of the PQC algorithms are complex; rendering their hardware modeling, evaluation, and benchmarking challenging. We developed a High-Level Synthesis (HLS) → ASIC flow for fast evaluation of Power, Area, Speed, and Security (PASS) trade-offs of the NIST round 2 PQC algorithms using an industry-standard design flow. In this paper, we discuss this flow and the preliminary results on some of the PQC signature algorithms.

Original languageEnglish (US)
Title of host publicationProceedings - 2019 IEEE International Conference on Computer Design, ICCD 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages337-340
Number of pages4
ISBN (Electronic)9781538666487
DOIs
StatePublished - Nov 2019
Event37th IEEE International Conference on Computer Design, ICCD 2019 - Abu Dhabi, United Arab Emirates
Duration: Nov 17 2019Nov 20 2019

Publication series

NameProceedings - 2019 IEEE International Conference on Computer Design, ICCD 2019

Conference

Conference37th IEEE International Conference on Computer Design, ICCD 2019
CountryUnited Arab Emirates
CityAbu Dhabi
Period11/17/1911/20/19

Keywords

  • Hardware implementation PQC
  • Hardware implementation of PQC
  • PQC algorithm
  • Signature scheme hardware implementation

ASJC Scopus subject areas

  • Information Systems and Management
  • Computer Networks and Communications
  • Control and Optimization
  • Hardware and Architecture

Fingerprint Dive into the research topics of 'Power, area, speed, and security (PASS) trade-offs of NIST PQC signature candidates using a C to ASIC design flow'. Together they form a unique fingerprint.

  • Cite this

    Soni, D., Nabeel, M., Basu, K., & Karri, R. (2019). Power, area, speed, and security (PASS) trade-offs of NIST PQC signature candidates using a C to ASIC design flow. In Proceedings - 2019 IEEE International Conference on Computer Design, ICCD 2019 (pp. 337-340). [8988781] (Proceedings - 2019 IEEE International Conference on Computer Design, ICCD 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICCD46524.2019.00054