Power Density-Aware Resource Management for Heterogeneous Tiled Multicores

Heba Khdr, Santiago Pagani, Éricles Sousa, Vahid Lari, Anuj Pathania, Frank Hannig, Muhammad Shafique, Jürgen Teich, Jörg Henkel

Research output: Contribution to journalArticlepeer-review

Abstract

Increasing power densities have led to the dark silicon era, for which heterogeneous multicores with different power and performance characteristics are promising architectures. This paper focuses on maximizing the overall system performance under a critical temperature constraint for heterogeneous tiled multicores, where all cores or accelerators inside a tile share the same voltage and frequency levels. For such architectures, we present a resource management technique that introduces power density as a novel system level constraint, in order to avoid thermal violations. The proposed technique then assigns applications to tiles by choosing their degree of parallelism and the voltage/frequency levels of each tile, such that the power density constraint is satisfied. Moreover, our technique provides runtime adaptation of the power density constraint according to the characteristics of the executed applications, and reacting to workload changes at runtime. Thus, the available thermal headroom is exploited to maximize the overall system performance.

Original languageEnglish (US)
Article number7524768
Pages (from-to)488-501
Number of pages14
JournalIEEE Transactions on Computers
Volume66
Issue number3
DOIs
StatePublished - Mar 1 2017

Keywords

  • dark silicon
  • Heterogeneous multicores
  • low power design
  • power density
  • resource management
  • thermal management

ASJC Scopus subject areas

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture
  • Computational Theory and Mathematics

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