TY - GEN
T1 - Power-efficient accelerator allocation in adaptive dark silicon many-core systems
AU - Khan, Muhammad Usman Karim
AU - Shafique, Muhammad
AU - Henkel, Jorg
N1 - Publisher Copyright:
© 2015 EDAA.
Copyright:
Copyright 2020 Elsevier B.V., All rights reserved.
PY - 2015/4/22
Y1 - 2015/4/22
N2 - Modern many-core systems in the dark silicon era face the predicament of underutilized resources of the chip due to power constraints. Therefore, hardware accelerators are becoming popular as they can overcome this problem by exercising a part of the program on dedicated custom logic in an energy efficient way. However, efficient accelerator usage poses numerous challenges, like adaptations for accelerator's sharing schedule on the many-core systems under run-time varying scenarios. In this work, we propose a power-efficient accelerator allocation scheme for adaptive many-core systems that maximally utilizes and dynamically allocates a shared accelerator to competing cores, such that deadlines of the executing applications are met and the total power consumption of the overall system is minimized. The experimental results demonstrate power minimization and high accelerator utilization for a many-core system.
AB - Modern many-core systems in the dark silicon era face the predicament of underutilized resources of the chip due to power constraints. Therefore, hardware accelerators are becoming popular as they can overcome this problem by exercising a part of the program on dedicated custom logic in an energy efficient way. However, efficient accelerator usage poses numerous challenges, like adaptations for accelerator's sharing schedule on the many-core systems under run-time varying scenarios. In this work, we propose a power-efficient accelerator allocation scheme for adaptive many-core systems that maximally utilizes and dynamically allocates a shared accelerator to competing cores, such that deadlines of the executing applications are met and the total power consumption of the overall system is minimized. The experimental results demonstrate power minimization and high accelerator utilization for a many-core system.
UR - http://www.scopus.com/inward/record.url?scp=84945952570&partnerID=8YFLogxK
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U2 - 10.7873/date.2015.0925
DO - 10.7873/date.2015.0925
M3 - Conference contribution
AN - SCOPUS:84945952570
T3 - Proceedings -Design, Automation and Test in Europe, DATE
SP - 916
EP - 919
BT - Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015
Y2 - 9 March 2015 through 13 March 2015
ER -