Power efficient and workload balanced tiling for parallelized high efficiency video coding

Muhammad Shafique, Muhammad Usman Karim Khan, Jorg Henkel

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The increased workload of the High Efficiency Video Coding (HEVC) and processing of high resolution videos require parallelization of the encoding/decoding process. However, to efficiently utilize the hardware resources and power budgets in a many-core processor, workload balanced parallelization of HEVC encoding is of high importance. Further, minimizing the number of active cores for processing the given HEVC encoding workload is required to decrease the power consumption. In order to address the above challenges, this work presents a HEVC parallelization technique to adaptively determine the Tile partitioning while accounting for the compute capabilities of the underlying processing cores. Afterwards, it determines a mapping of Tiled-HEVC processing on different cores such that the number of compute cores is minimized, and hence reducing the power consumption. Experimental results demonstrate that in addition to reducing the total compute cores, our technique provides up to 14.4% power savings compared to state-of-the-art uniform Tile partitioning approach.

Original languageEnglish (US)
Title of host publication2014 IEEE International Conference on Image Processing, ICIP 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1253-1257
Number of pages5
ISBN (Electronic)9781479957514
DOIs
StatePublished - Jan 28 2014

Publication series

Name2014 IEEE International Conference on Image Processing, ICIP 2014

Keywords

  • High Efficiency Video Coding
  • many-core processor
  • Parallel architectures
  • power efficient designs

ASJC Scopus subject areas

  • Computer Vision and Pattern Recognition

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