TY - GEN
T1 - Power efficient and workload balanced tiling for parallelized high efficiency video coding
AU - Shafique, Muhammad
AU - Khan, Muhammad Usman Karim
AU - Henkel, Jorg
N1 - Publisher Copyright:
© 2014 IEEE.
Copyright:
Copyright 2016 Elsevier B.V., All rights reserved.
PY - 2014/1/28
Y1 - 2014/1/28
N2 - The increased workload of the High Efficiency Video Coding (HEVC) and processing of high resolution videos require parallelization of the encoding/decoding process. However, to efficiently utilize the hardware resources and power budgets in a many-core processor, workload balanced parallelization of HEVC encoding is of high importance. Further, minimizing the number of active cores for processing the given HEVC encoding workload is required to decrease the power consumption. In order to address the above challenges, this work presents a HEVC parallelization technique to adaptively determine the Tile partitioning while accounting for the compute capabilities of the underlying processing cores. Afterwards, it determines a mapping of Tiled-HEVC processing on different cores such that the number of compute cores is minimized, and hence reducing the power consumption. Experimental results demonstrate that in addition to reducing the total compute cores, our technique provides up to 14.4% power savings compared to state-of-the-art uniform Tile partitioning approach.
AB - The increased workload of the High Efficiency Video Coding (HEVC) and processing of high resolution videos require parallelization of the encoding/decoding process. However, to efficiently utilize the hardware resources and power budgets in a many-core processor, workload balanced parallelization of HEVC encoding is of high importance. Further, minimizing the number of active cores for processing the given HEVC encoding workload is required to decrease the power consumption. In order to address the above challenges, this work presents a HEVC parallelization technique to adaptively determine the Tile partitioning while accounting for the compute capabilities of the underlying processing cores. Afterwards, it determines a mapping of Tiled-HEVC processing on different cores such that the number of compute cores is minimized, and hence reducing the power consumption. Experimental results demonstrate that in addition to reducing the total compute cores, our technique provides up to 14.4% power savings compared to state-of-the-art uniform Tile partitioning approach.
KW - High Efficiency Video Coding
KW - many-core processor
KW - Parallel architectures
KW - power efficient designs
UR - http://www.scopus.com/inward/record.url?scp=84962397872&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84962397872&partnerID=8YFLogxK
U2 - 10.1109/ICIP.2014.7025250
DO - 10.1109/ICIP.2014.7025250
M3 - Conference contribution
AN - SCOPUS:84962397872
T3 - 2014 IEEE International Conference on Image Processing, ICIP 2014
SP - 1253
EP - 1257
BT - 2014 IEEE International Conference on Image Processing, ICIP 2014
PB - Institute of Electrical and Electronics Engineers Inc.
ER -