Power-efficient load-balancing on heterogeneous computing platforms

Muhammad Usman Karim Khan, Muhammad Shafique, Apratim Gupta, Thomas Schumann, Jörg Henkel

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In order to address the throughput constraints of the system at minimal power consumption, the workload of computing nodes should be balanced. This requires accounting for the underlying hardware characteristics and throughput sustainable by these nodes. This work provides a workload distribution and balancing methodology of a divisible load under a throughput constraint, on heterogeneous nodes. The power efficiency of each node is considered during load distribution. For load balancing, the frequency of the node is determined which just fulfills the timing requirement. Compared to a state-of-the-art-scheme, our scheme results in up to 64% performance improvement for the benchmarks evaluated in this paper.

Original languageEnglish (US)
Title of host publicationProceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1469-1472
Number of pages4
ISBN (Electronic)9783981537062
StatePublished - Apr 25 2016
Event19th Design, Automation and Test in Europe Conference and Exhibition, DATE 2016 - Dresden, Germany
Duration: Mar 14 2016Mar 18 2016

Publication series

NameProceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016

Other

Other19th Design, Automation and Test in Europe Conference and Exhibition, DATE 2016
CountryGermany
CityDresden
Period3/14/163/18/16

Keywords

  • DVFS
  • Hardware Accelerator
  • Heterogeneous Computing
  • Load Balancing
  • Power-Efficiency

ASJC Scopus subject areas

  • Hardware and Architecture
  • Safety, Risk, Reliability and Quality

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