Power optimization for universal hash function data path using divide-and-concatenate technique

Bo Yang, Ramesh Karri

Research output: Contribution to journalArticle

Abstract

We present an architecture level low-power design technique called divide and concatenate for universal hash functions based on the following observations. 1) The power consumption of a w -bit array multiplier and associated universal hash data path decreases as O(w4) if its clock rate remains constant. 2) Two universal hash functions are equivalent if they have the same collision probability property. In the proposed approach, we divide a w-bit data path (with collision probability 2-w) into two/four w/2-bit data paths (each with collision probability 2-w/2) and concatenate their results to construct an equivalent w-bit data path (with a collision probability 2-w). A popular low-power technique that uses parallel data paths saves 62.10% dynamic power consumption incurring 102% area overhead. In contrast, the divide-and-concatenate technique saves 55.44% dynamic power consumption with only 16% area overhead.

Original languageEnglish (US)
Pages (from-to)1763-1769
Number of pages7
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume26
Issue number10
DOIs
StatePublished - Oct 2007

Keywords

  • Divide and concatenate
  • Power optimization
  • Universal hash function

ASJC Scopus subject areas

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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