TY - GEN
T1 - Power-side-channel analysis of carbon nanotube FET based design
AU - Suresh, Chandra K.H.
AU - Mazumdar, Bodhisatwa
AU - Ali, Sk Subidh
AU - Sinanoglu, Ozgur
N1 - Publisher Copyright:
© 2016 IEEE.
PY - 2016/10/20
Y1 - 2016/10/20
N2 - Continuous scaling of CMOS technology beyond sub-nanometer region has aggravated short-channel effects, resulting in increased leakage current and high power densities. Furthermore, elevated leakage current and power density render CMOS based security-critical applications vulnerable to power-side-channel attacks. Carbon Nanotubes (CNT) is a promising alternative to CMOS technology. It offers superior transport properties, excellent thermal conductivities, high current capacities, and low power densities. Besides area, power and performance, adherence to hardware security aspects have become an important criteria today. In this work, we present the first study on power-side-channel analysis of ciphers implemented using CNTFETs. Our simulation results show that for 130 power traces, the simple power analysis (SPA) attack success rate is less than 0.35 for CNTFET based ciphers, whereas it is greater than 0.95 for CMOS based ciphers. For correlation power analysis, the difference of correlation coefficient of the correct key and closest wrong key guess is 1.3 for CMOS based design, and less than 0.56 for CNTFET based ciphers for 20,000 power traces, which implies lesser distinguishability of correct key in case of CNTFETs. These results indicate that CNT offers a higher resilience to power-side-channel attacks than CMOS.
AB - Continuous scaling of CMOS technology beyond sub-nanometer region has aggravated short-channel effects, resulting in increased leakage current and high power densities. Furthermore, elevated leakage current and power density render CMOS based security-critical applications vulnerable to power-side-channel attacks. Carbon Nanotubes (CNT) is a promising alternative to CMOS technology. It offers superior transport properties, excellent thermal conductivities, high current capacities, and low power densities. Besides area, power and performance, adherence to hardware security aspects have become an important criteria today. In this work, we present the first study on power-side-channel analysis of ciphers implemented using CNTFETs. Our simulation results show that for 130 power traces, the simple power analysis (SPA) attack success rate is less than 0.35 for CNTFET based ciphers, whereas it is greater than 0.95 for CMOS based ciphers. For correlation power analysis, the difference of correlation coefficient of the correct key and closest wrong key guess is 1.3 for CMOS based design, and less than 0.56 for CNTFET based ciphers for 20,000 power traces, which implies lesser distinguishability of correct key in case of CNTFETs. These results indicate that CNT offers a higher resilience to power-side-channel attacks than CMOS.
KW - CPA
KW - Carbon Nanotube (CNT) Field Effect Transistor (CNTFET)
KW - Cipher
KW - Hardware Security
KW - Power Delay Product (PDP)
KW - SPA
UR - http://www.scopus.com/inward/record.url?scp=84997354356&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84997354356&partnerID=8YFLogxK
U2 - 10.1109/IOLTS.2016.7604705
DO - 10.1109/IOLTS.2016.7604705
M3 - Conference contribution
AN - SCOPUS:84997354356
T3 - 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design, IOLTS 2016
SP - 215
EP - 218
BT - 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design, IOLTS 2016
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 22nd IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2016
Y2 - 4 July 2016 through 6 July 2016
ER -