TY - JOUR
T1 - Process-driven variability analysis of single and multiple voltage-frequency island latency-constrained systems
AU - Marculescu, Diana
AU - Garg, Siddharth
N1 - Funding Information:
Manuscript received March 14, 2007; revised July 2, 2007 and October 22, 2007. This work was supported in part by the Semiconductor Research Corporation under Contract 2005-HJ-1314. This paper was recommended by Associate Editor L. Benini. The authors are with Carnegie Mellon University, Pittsburgh, PA 15213 USA (e-mail: [email protected]; [email protected]). Digital Object Identifier 10.1109/TCAD.2008.917969
PY - 2008/5
Y1 - 2008/5
N2 - The problem of determining bounds for application completion times running on generic systems comprising single or multiple voltagefrequency islands (VFIs) with arbitrary topologies is addressed in the context of manufacturing-process- driven variability. The approach provides an exact solution for the system-level timing yield in synchronous single-voltage (SSV) and VFI systems with an underlying tree-based topology and a tight upper bound for generic non-tree-based topologies. The results show that: 1) timing yield for the overall source-to-sink completion time for generic systems can be modeled in an exact manner for both SSV and VFI systems and 2) multiple-VFI latency-constrained systems can achieve up to two times higher timing yield than their SSV counterparts. The results are formally proven and are supported by experimental results on two embedded applications, namely, a software-defined radio and a Moving Pictures Expert Group 2 encoder.
AB - The problem of determining bounds for application completion times running on generic systems comprising single or multiple voltagefrequency islands (VFIs) with arbitrary topologies is addressed in the context of manufacturing-process- driven variability. The approach provides an exact solution for the system-level timing yield in synchronous single-voltage (SSV) and VFI systems with an underlying tree-based topology and a tight upper bound for generic non-tree-based topologies. The results show that: 1) timing yield for the overall source-to-sink completion time for generic systems can be modeled in an exact manner for both SSV and VFI systems and 2) multiple-VFI latency-constrained systems can achieve up to two times higher timing yield than their SSV counterparts. The results are formally proven and are supported by experimental results on two embedded applications, namely, a software-defined radio and a Moving Pictures Expert Group 2 encoder.
KW - Design variability
KW - Performance analysis
KW - Voltage-frequency islands
UR - http://www.scopus.com/inward/record.url?scp=42649086793&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=42649086793&partnerID=8YFLogxK
U2 - 10.1109/TCAD.2008.917969
DO - 10.1109/TCAD.2008.917969
M3 - Article
AN - SCOPUS:42649086793
SN - 0278-0070
VL - 27
SP - 893
EP - 904
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IS - 5
M1 - 4492838
ER -