Process variation aware performance modeling and dynamic power management for multi-core systems

Siddharth Garg, Diana Marculescu, Sebastian X. Herbert

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Emerging multi-core platforms are increasingly impacted by the manufacturing process variations that introduce core-to-core and chip-to-chip differences in their power and performance characteristics. This can result in unacceptable yield loss since a large fraction of manufactured parts may not meet the design specifications. In this work, we present some promising, recently proposed solutions to mitigate the impact of process variations on multi-core platforms that deal with variability aware performance modeling, and static and dynamic power reduction. These solutions demonstrate the significant benefits that can be reaped if variability information is considered at the micro-architecture and system level design abstractions.

Original languageEnglish (US)
Title of host publication2010 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2010
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages89-92
Number of pages4
ISBN (Print)9781424481927
DOIs
StatePublished - 2010
Event2010 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2010 - San Jose, CA, United States
Duration: Nov 7 2010Nov 11 2010

Publication series

NameIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
ISSN (Print)1092-3152

Other

Other2010 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2010
Country/TerritoryUnited States
CitySan Jose, CA
Period11/7/1011/11/10

ASJC Scopus subject areas

  • Software
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design

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