Protect your chip design intellectual property: An overview

Johann Knechtel, Satwik Patnaik, Ozgur Sinanoglu

Research output: Contribution to conferencePaperpeer-review

Abstract

The increasing cost of integrated circuit (IC) fabrication has driven most companies to "go fabless" over time. The corresponding outsourcing trend gave rise to various attack vectors, e.g., illegal overproduction of ICs, piracy of the design intellectual property (IP), or insertion of hardware Trojans (HTs). These attacks are possibly conducted by untrusted entities residing all over the supply chain, ranging from untrusted foundries, test facilities, even to end-users. To overcome this multitude of threats, various techniques have been proposed over the past decade. In this paper, we review the landscape of IP protection techniques, which can be classified into logic locking, layout camouflaging, and split manufacturing. We discuss the history of these techniques, followed by state-of-the-art advancements, relevant limitations, and scope for future work.

Original languageEnglish (US)
Pages211-216
Number of pages6
DOIs
StatePublished - 2019
Event2019 International Conference Omni-Layer Intelligent Systems, COINS 2019 - Crete, Greece
Duration: May 5 2019May 7 2019

Conference

Conference2019 International Conference Omni-Layer Intelligent Systems, COINS 2019
CountryGreece
CityCrete
Period5/5/195/7/19

Keywords

  • Layout Camouflaging
  • Logic Locking
  • Split Manufacturing

ASJC Scopus subject areas

  • Software
  • Human-Computer Interaction
  • Computer Vision and Pattern Recognition
  • Computer Networks and Communications

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