Protecting Hardware IP Cores During High-Level Synthesis

Christian Pilato, Donatella Sciuto, Francesco Regazzoni, Siddharth Garg, Ramesh Karri

Research output: Chapter in Book/Report/Conference proceedingChapter


Intellectual property (IP) theft is one of the major concerns for the economy of semiconductor companies, costing billions of dollars every year. To make unauthorized IP copies, an attacker must reverse engineer and replicate the functionality of the given chip design. While the existing IP protection techniques aim at manipulating HDL descriptions to thwart the reverse engineering process, they focus on the given implementation and fail in hiding all details of the chip functionality. We propose a comprehensive solution to address this problem during high-level synthesis in order to apply obfuscation at the algorithm level. Our solution includes several key-based transformations that are applied during component generation to make reverse engineering harder during chip fabrication, while the key is later provided to the circuit to unlock the functionality. We show that our method is a promising approach to obfuscate large-scale designs despite the obfuscation overhead.

Original languageEnglish (US)
Title of host publicationBehavioral Synthesis for Hardware Security
PublisherSpringer International Publishing
Number of pages21
ISBN (Electronic)9783030788414
ISBN (Print)9783030788407
StatePublished - Jan 1 2022


  • Hardware security
  • High-level synthesis
  • Integrated circuits
  • IP protection
  • Obfuscation
  • Untrusted foundry

ASJC Scopus subject areas

  • General Engineering
  • General Computer Science


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