Quantifying acceleration: Power/performance trade-offs of application kernels in hardware

Brandon Reagen, Yakun Sophia Shao, Gu Yeon Wei, David Brooks

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

As the traditional performance gains of technology scaling diminish, one of the most promising directions is building special purpose fixed function hardware blocks, commonly referred to as accelerators. Accelerators have become prevalent in industrial SoC designs for their low power, high performance potential. In this work we explore thousands of implementations of classical software workloads in hardware. This thorough, detailed design space search of hardware accelerators gives architects a quantitative way to reason about the differences in implementations. The exploration presented in this work shows that the space is full of poor design choices. By thoroughly analyzing each benchmark, we show which provide the most performance when implemented in hardware given a fixed power budget and explain which design techniques work best for each workload.

Original languageEnglish (US)
Title of host publicationProceedings of the International Symposium on Low Power Electronics and Design, ISLPED 2013
Pages395-400
Number of pages6
DOIs
StatePublished - 2013
Event2013 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED 2013 - Beijing, China
Duration: Sep 4 2013Sep 6 2013

Publication series

NameProceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)1533-4678

Conference

Conference2013 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED 2013
CountryChina
CityBeijing
Period9/4/139/6/13

Keywords

  • Accelerator
  • Design Space Exploration
  • Power Performance Trade-offs

ASJC Scopus subject areas

  • Engineering(all)

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