TY - GEN
T1 - Quantifying the Overheads of Modular Multiplication
AU - Soni, Deepraj
AU - Nabeel, Mohammed
AU - Neda, Negar
AU - Karri, Ramesh
AU - Maniatakos, Michail
AU - Reagen, Brandon
N1 - Funding Information:
This work is supported in part by NSF award 2016650. Additionally, this research was developed with funding from the Defense Advanced Research Projects Agency (DARPA), under the Data Protection in Virtual Environments (DPRIVE) program, contract HR0011-21-9-0003. Finally, we are grateful to the reviewers for their valuable input, which has significantly enhanced the quality of the paper.
Publisher Copyright:
© 2023 IEEE.
PY - 2023
Y1 - 2023
N2 - As security and privacy continue to grow in importance, new techniques, including fully homomorphic encryption (FHE) and post-quantum cryptography (PQC), have emerged to provide new capabilities. Many of these techniques are based on the ring learning with errors problem and operate over rings. Elements of a ring are computed using modular arithmetic, with modular multiplication being a primary component. These components are far more complex than standard integer computing, especially when working with large bit widths. As FHE and PQC become increasingly popular, the need for well-designed and optimized modular multipliers also grows in importance. In this paper, we analyze the power, area, performance, energy, and thermal characteristics of two commonly used modular multipliers: Barrett (bit parallel) and Interleaved (bit parallel). To understand these multipliers' characteristics, this study provides necessary insights into the sources of area, power, frequency, and energy overhead, considering a range of different bit widths (16-256). This paper rigorously analyzes the sub-blocks of modular multipliers and their contributions to overall power, performance, and area (PPA).
AB - As security and privacy continue to grow in importance, new techniques, including fully homomorphic encryption (FHE) and post-quantum cryptography (PQC), have emerged to provide new capabilities. Many of these techniques are based on the ring learning with errors problem and operate over rings. Elements of a ring are computed using modular arithmetic, with modular multiplication being a primary component. These components are far more complex than standard integer computing, especially when working with large bit widths. As FHE and PQC become increasingly popular, the need for well-designed and optimized modular multipliers also grows in importance. In this paper, we analyze the power, area, performance, energy, and thermal characteristics of two commonly used modular multipliers: Barrett (bit parallel) and Interleaved (bit parallel). To understand these multipliers' characteristics, this study provides necessary insights into the sources of area, power, frequency, and energy overhead, considering a range of different bit widths (16-256). This paper rigorously analyzes the sub-blocks of modular multipliers and their contributions to overall power, performance, and area (PPA).
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U2 - 10.1109/ISLPED58423.2023.10244324
DO - 10.1109/ISLPED58423.2023.10244324
M3 - Conference contribution
AN - SCOPUS:85173091834
T3 - Proceedings of the International Symposium on Low Power Electronics and Design
BT - 2023 IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2023
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2023 IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2023
Y2 - 7 August 2023 through 8 August 2023
ER -