The asynchronous transfer mode (ATM) technique has been widely accepted as a flexible and effective scheme to transport various traffic over the future broadband network. To fully utilize network resources while still providing satisfactory quality of service (QOS) to all network users, prioritizing users' traffic according to their service requirements becomes necessary. During the call setup, each service can be assigned a service class determined by a delay priority and a loss priority. A queue manager in ATM network nodes will schedule ATM cells' departing and discarding sequence based on their delay and loss priorities. Most queue management schemes that have been proposed so far only consider either one of these two priority types. In this paper, the queue manager treats multiple delay and loss priorities simultaneously. Moreover, a cell discarding strategy, called push out which allows the buffer to be completely shared by all service classes, has been adopted in the queue manager. We propose a practical architecture to implement the queue manager, facilitated by a new VLSI chip, an enhanced version of the existing Sequencer VLSI chip.