RAISE: Reliability-Aware Instruction SchEduling for unreliable hardware

Semeen Rehman; Muhammad Shafique; Florian Kriebel; Jörg Henkel

doi:10.1109/ASPDAC.2012.6165040

RAISE: Reliability-Aware Instruction SchEduling for unreliable hardware

Semeen Rehman, Muhammad Shafique, Florian Kriebel, Jörg Henkel

Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A compile-time Reliability-Aware Instruction SchEduling (RAISE) scheme is presented, which takes into account the spatial and temporal vulnerabilities of different processor resources (pipeline, register file, etc.) used during the execution of different instructions. It reduces the software program's susceptibility towards failures by minimizing the occupancy cycles of critical instructions inside the pipeline stages in addition to reducing the vulnerable periods of their operands. To facilitate RAISE, a novel technique for static reliability estimation during compilation is presented (i.e. before instructions scheduling). Compared to state-of-the-art reliability-aware instruction schedulers, our scheme provides up to 32.7% reduced software program failures over three different fault rates.

Original language	English (US)
Title of host publication	ASP-DAC 2012 - 17th Asia and South Pacific Design Automation Conference
Pages	671-676
Number of pages	6
DOIs	https://doi.org/10.1109/ASPDAC.2012.6165040
State	Published - 2012
Event	17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012 - Sydney, NSW, Australia Duration: Jan 30 2012 → Feb 2 2012

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference	17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012
Country/Territory	Australia
City	Sydney, NSW
Period	1/30/12 → 2/2/12

ASJC Scopus subject areas

Computer Science Applications
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

Access to Document

10.1109/ASPDAC.2012.6165040

Cite this

RAISE: Reliability-Aware Instruction SchEduling for unreliable hardware. / Rehman, Semeen; Shafique, Muhammad; Kriebel, Florian et al.
ASP-DAC 2012 - 17th Asia and South Pacific Design Automation Conference. 2012. p. 671-676 6165040 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Rehman, S, Shafique, M, Kriebel, F & Henkel, J 2012, RAISE: Reliability-Aware Instruction SchEduling for unreliable hardware. in ASP-DAC 2012 - 17th Asia and South Pacific Design Automation Conference., 6165040, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, pp. 671-676, 17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012, Sydney, NSW, Australia, 1/30/12. https://doi.org/10.1109/ASPDAC.2012.6165040

@inproceedings{9aff4261c88d4f2185387daaaa559926,

title = "RAISE: Reliability-Aware Instruction SchEduling for unreliable hardware",

abstract = "A compile-time Reliability-Aware Instruction SchEduling (RAISE) scheme is presented, which takes into account the spatial and temporal vulnerabilities of different processor resources (pipeline, register file, etc.) used during the execution of different instructions. It reduces the software program's susceptibility towards failures by minimizing the occupancy cycles of critical instructions inside the pipeline stages in addition to reducing the vulnerable periods of their operands. To facilitate RAISE, a novel technique for static reliability estimation during compilation is presented (i.e. before instructions scheduling). Compared to state-of-the-art reliability-aware instruction schedulers, our scheme provides up to 32.7% reduced software program failures over three different fault rates.",

author = "Semeen Rehman and Muhammad Shafique and Florian Kriebel and J{\"o}rg Henkel",

year = "2012",

doi = "10.1109/ASPDAC.2012.6165040",

language = "English (US)",

isbn = "9781467307727",

series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

pages = "671--676",

booktitle = "ASP-DAC 2012 - 17th Asia and South Pacific Design Automation Conference",

}

TY - GEN

T1 - RAISE

T2 - 17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012

AU - Rehman, Semeen

AU - Shafique, Muhammad

AU - Kriebel, Florian

AU - Henkel, Jörg

PY - 2012

Y1 - 2012

N2 - A compile-time Reliability-Aware Instruction SchEduling (RAISE) scheme is presented, which takes into account the spatial and temporal vulnerabilities of different processor resources (pipeline, register file, etc.) used during the execution of different instructions. It reduces the software program's susceptibility towards failures by minimizing the occupancy cycles of critical instructions inside the pipeline stages in addition to reducing the vulnerable periods of their operands. To facilitate RAISE, a novel technique for static reliability estimation during compilation is presented (i.e. before instructions scheduling). Compared to state-of-the-art reliability-aware instruction schedulers, our scheme provides up to 32.7% reduced software program failures over three different fault rates.

AB - A compile-time Reliability-Aware Instruction SchEduling (RAISE) scheme is presented, which takes into account the spatial and temporal vulnerabilities of different processor resources (pipeline, register file, etc.) used during the execution of different instructions. It reduces the software program's susceptibility towards failures by minimizing the occupancy cycles of critical instructions inside the pipeline stages in addition to reducing the vulnerable periods of their operands. To facilitate RAISE, a novel technique for static reliability estimation during compilation is presented (i.e. before instructions scheduling). Compared to state-of-the-art reliability-aware instruction schedulers, our scheme provides up to 32.7% reduced software program failures over three different fault rates.

UR - http://www.scopus.com/inward/record.url?scp=84859942949&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84859942949&partnerID=8YFLogxK

U2 - 10.1109/ASPDAC.2012.6165040

DO - 10.1109/ASPDAC.2012.6165040

M3 - Conference contribution

AN - SCOPUS:84859942949

SN - 9781467307727

T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

SP - 671

EP - 676

BT - ASP-DAC 2012 - 17th Asia and South Pacific Design Automation Conference

Y2 - 30 January 2012 through 2 February 2012

ER -

RAISE: Reliability-Aware Instruction SchEduling for unreliable hardware

Abstract

Publication series

Conference

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this