RAISE: Reliability-Aware Instruction SchEduling for unreliable hardware

Semeen Rehman, Muhammad Shafique, Florian Kriebel, Jörg Henkel

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A compile-time Reliability-Aware Instruction SchEduling (RAISE) scheme is presented, which takes into account the spatial and temporal vulnerabilities of different processor resources (pipeline, register file, etc.) used during the execution of different instructions. It reduces the software program's susceptibility towards failures by minimizing the occupancy cycles of critical instructions inside the pipeline stages in addition to reducing the vulnerable periods of their operands. To facilitate RAISE, a novel technique for static reliability estimation during compilation is presented (i.e. before instructions scheduling). Compared to state-of-the-art reliability-aware instruction schedulers, our scheme provides up to 32.7% reduced software program failures over three different fault rates.

Original languageEnglish (US)
Title of host publicationASP-DAC 2012 - 17th Asia and South Pacific Design Automation Conference
Pages671-676
Number of pages6
DOIs
StatePublished - 2012
Event17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012 - Sydney, NSW, Australia
Duration: Jan 30 2012Feb 2 2012

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012
CountryAustralia
CitySydney, NSW
Period1/30/122/2/12

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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