Rapid prototyping of fault tolerant VLSI systems

Ramesh Karri, Karin Hogstedt, Alex Orailoglu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we relate fault-tolerance constraints to chip area and present a methodology for rapidly compiling an algorithmic description into area-efficient fault-tolerant VLSI ICs. Whereas detection and recovery from environment induced transient faults is accomplished by checkpointing and rollback, uninterrupted operation for the lifetime of a mission is ensured by injecting redundancy. Towards validating this methodology, we synthesized fault tolerant implementations of a 16-point FIR filter starting from an algorithmic description. These fault-tolerant designs were then critically appraised.

Original languageEnglish (US)
Title of host publicationProceedings of the IEEE International Symposium on High-Level Synthesis
Editors Anon
PublisherPubl by IEEE
Pages126-131
Number of pages6
ISBN (Print)0818657855
StatePublished - Jan 1 1994
EventProceedings of the 7th International Symposium on High-Level Synthesis - Niagara-on-the-Lake, Ont, Can
Duration: May 18 1994May 20 1994

Publication series

NameProceedings of the IEEE International Symposium on High-Level Synthesis

Other

OtherProceedings of the 7th International Symposium on High-Level Synthesis
CityNiagara-on-the-Lake, Ont, Can
Period5/18/945/20/94

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • Cite this

    Karri, R., Hogstedt, K., & Orailoglu, A. (1994). Rapid prototyping of fault tolerant VLSI systems. In Anon (Ed.), Proceedings of the IEEE International Symposium on High-Level Synthesis (pp. 126-131). (Proceedings of the IEEE International Symposium on High-Level Synthesis). Publ by IEEE.