TY - GEN
T1 - Reconciling the IC test and security dichotomy
AU - Sinanoglu, O.
AU - Karimi, N.
AU - Rajendran, J.
AU - Karri, R.
AU - Jin, Y.
AU - Huang, K.
AU - Makris, Y.
PY - 2013
Y1 - 2013
N2 - Many of the design companies cannot afford owning and acquiring expensive foundries and hence, go fabless and outsource their design fabrication to foundries that are potentially untrustwrothy. This globalization of Integrated Circuit (IC) design flow has introduced security vulnerabilities. If a design is fabricated in a foundry that is outside the direct control of the (fabless) design house, reverse engineering, malicious circuit modification, and Intellectual Property (IP) piracy are possible. In this tutorial, we elaborate on these and similar hardware security threats by making connections to VLSI testing. We cover design-for-trust techniques, such as logic encryption, aging acceleration attacks, and statistical methods that help identify Trojan'ed and counterfeit ICs.
AB - Many of the design companies cannot afford owning and acquiring expensive foundries and hence, go fabless and outsource their design fabrication to foundries that are potentially untrustwrothy. This globalization of Integrated Circuit (IC) design flow has introduced security vulnerabilities. If a design is fabricated in a foundry that is outside the direct control of the (fabless) design house, reverse engineering, malicious circuit modification, and Intellectual Property (IP) piracy are possible. In this tutorial, we elaborate on these and similar hardware security threats by making connections to VLSI testing. We cover design-for-trust techniques, such as logic encryption, aging acceleration attacks, and statistical methods that help identify Trojan'ed and counterfeit ICs.
UR - http://www.scopus.com/inward/record.url?scp=84883327945&partnerID=8YFLogxK
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U2 - 10.1109/ETS.2013.6569368
DO - 10.1109/ETS.2013.6569368
M3 - Conference contribution
AN - SCOPUS:84883327945
SN - 9781467363778
T3 - Proceedings - 2013 18th IEEE European Test Symposium, ETS 2013
BT - Proceedings - 2013 18th IEEE European Test Symposium, ETS 2013
T2 - 2013 18th IEEE European Test Symposium, ETS 2013
Y2 - 27 May 2013 through 30 May 2013
ER -