Reconciling the IC test and security dichotomy

O. Sinanoglu, N. Karimi, J. Rajendran, R. Karri, Y. Jin, K. Huang, Y. Makris

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Many of the design companies cannot afford owning and acquiring expensive foundries and hence, go fabless and outsource their design fabrication to foundries that are potentially untrustwrothy. This globalization of Integrated Circuit (IC) design flow has introduced security vulnerabilities. If a design is fabricated in a foundry that is outside the direct control of the (fabless) design house, reverse engineering, malicious circuit modification, and Intellectual Property (IP) piracy are possible. In this tutorial, we elaborate on these and similar hardware security threats by making connections to VLSI testing. We cover design-for-trust techniques, such as logic encryption, aging acceleration attacks, and statistical methods that help identify Trojan'ed and counterfeit ICs.

Original languageEnglish (US)
Title of host publicationProceedings - 2013 18th IEEE European Test Symposium, ETS 2013
DOIs
StatePublished - 2013
Event2013 18th IEEE European Test Symposium, ETS 2013 - Avignon, France
Duration: May 27 2013May 30 2013

Publication series

NameProceedings - 2013 18th IEEE European Test Symposium, ETS 2013

Other

Other2013 18th IEEE European Test Symposium, ETS 2013
CountryFrance
CityAvignon
Period5/27/135/30/13

ASJC Scopus subject areas

  • Software

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