TY - JOUR
T1 - Regaining trust in VLSI design
T2 - Design-for-trust techniques
AU - Rajendran, Jeyavijayan
AU - Sinanoglu, Ozgur
AU - Karri, Ramesh
N1 - Copyright:
Copyright 2020 Elsevier B.V., All rights reserved.
PY - 2014/8
Y1 - 2014/8
N2 - Designers use third-party intellectual property (IP) cores and outsource various steps in their integrated circuit (IC) design flow, including fabrication. As a result, security vulnerabilities have been emerging, forcing IC designers and end-users to reevaluate their trust in hardware. If an attacker gets hold of an unprotected design, attacks such as reverse engineering, insertion of malicious circuits, and IP piracy are possible. In this paper, we shed light on the vulnerabilities in very large scale integration (VLSI) design and fabrication flow, and survey design-for-trust (DfTr) techniques that aim at regaining trust in IC design. We elaborate on four DfTr techniques: logic encryption, split manufacturing, IC camouflaging, and Trojan activation. These techniques have been developed by reusing VLSI test principles.
AB - Designers use third-party intellectual property (IP) cores and outsource various steps in their integrated circuit (IC) design flow, including fabrication. As a result, security vulnerabilities have been emerging, forcing IC designers and end-users to reevaluate their trust in hardware. If an attacker gets hold of an unprotected design, attacks such as reverse engineering, insertion of malicious circuits, and IP piracy are possible. In this paper, we shed light on the vulnerabilities in very large scale integration (VLSI) design and fabrication flow, and survey design-for-trust (DfTr) techniques that aim at regaining trust in IC design. We elaborate on four DfTr techniques: logic encryption, split manufacturing, IC camouflaging, and Trojan activation. These techniques have been developed by reusing VLSI test principles.
KW - Design automation
KW - design for testability
KW - security
UR - http://www.scopus.com/inward/record.url?scp=84905109260&partnerID=8YFLogxK
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U2 - 10.1109/JPROC.2014.2332154
DO - 10.1109/JPROC.2014.2332154
M3 - Article
AN - SCOPUS:84905109260
VL - 102
SP - 1266
EP - 1282
JO - Proceedings of the IEEE
JF - Proceedings of the IEEE
SN - 0018-9219
IS - 8
M1 - 6856167
ER -