Regaining trust in VLSI design: Design-for-trust techniques

Jeyavijayan Rajendran, Ozgur Sinanoglu, Ramesh Karri

Research output: Contribution to journalArticle

Abstract

Designers use third-party intellectual property (IP) cores and outsource various steps in their integrated circuit (IC) design flow, including fabrication. As a result, security vulnerabilities have been emerging, forcing IC designers and end-users to reevaluate their trust in hardware. If an attacker gets hold of an unprotected design, attacks such as reverse engineering, insertion of malicious circuits, and IP piracy are possible. In this paper, we shed light on the vulnerabilities in very large scale integration (VLSI) design and fabrication flow, and survey design-for-trust (DfTr) techniques that aim at regaining trust in IC design. We elaborate on four DfTr techniques: logic encryption, split manufacturing, IC camouflaging, and Trojan activation. These techniques have been developed by reusing VLSI test principles.

Original languageEnglish (US)
Article number6856167
Pages (from-to)1266-1282
Number of pages17
JournalProceedings of the IEEE
Volume102
Issue number8
DOIs
StatePublished - Aug 2014

Keywords

  • Design automation
  • design for testability
  • security

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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