Abstract
A fault-secure datapath either generates a correct result or signals an error. This paper presents a register transfer level Concurrent Error Detection (CED) technique that uses hybrid time and hardware redundancy to optimize the time and area overhead associated with fault security. The proposed technique combines the idle computation cycles in a datapath with selective breaking of data dependences of the normal computation. Designers can trade-off time and hardware overhead by varying these design parameters. We present an algorithm to synthesize fault secure designs and validate it using Synopsys Behavioral Compiler.
| Original language | English (US) |
|---|---|
| Title of host publication | IEEE International Test Conference (TC) |
| Pages | 902-911 |
| Number of pages | 10 |
| State | Published - 2003 |
| Event | Proceedings International Test Conference 2003 - Charlotte, NC, United States Duration: Sep 30 2003 → Oct 2 2003 |
Other
| Other | Proceedings International Test Conference 2003 |
|---|---|
| Country/Territory | United States |
| City | Charlotte, NC |
| Period | 9/30/03 → 10/2/03 |
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering
- Hardware and Architecture