Register transfer level concurrent error detection in elliptic curve crypto implementations

Richard Stern; Nikhil Joshi; Kaijie Wu; Ramesh Karri

doi:10.1109/FDTC.2007.4318991

Register transfer level concurrent error detection in elliptic curve crypto implementations

Richard Stern, Nikhil Joshi, Kaijie Wu, Ramesh Karri

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In this paper we present an Register Transfer Level (RTL) Concurrent Error Detection (CED) technique targeting hardware implementations of Elliptic Curve Cryptography (ECC). The proposed mixed hardware-and time-redundancy based CED techniques use the mathematical properties of the underlying Galois Field as well as the ECC primitives to detect both soft errors and permanent faults with low area overhead. Results for sequential implementations of GF multiplication and inverse operations yielded an area overhead of 30% and a time overhead of 120%.

Original language	English (US)
Title of host publication	Proceedings Workshop on Fault Diagnosis and Tolerance in Cryptography, FDTC 2007
Pages	112-119
Number of pages	8
DOIs	https://doi.org/10.1109/FDTC.2007.4318991
State	Published - 2007
Event	4th International Workshop on Fault Diagnosis and Tolerance in Cryptography, FDTC 2007 - Vienna, Austria Duration: Sep 10 2007 → Sep 10 2007

Publication series

Name	Proceedings Workshop on Fault Diagnosis and Tolerance in Cryptography, FDTC 2007

Other

Other	4th International Workshop on Fault Diagnosis and Tolerance in Cryptography, FDTC 2007
Country/Territory	Austria
City	Vienna
Period	9/10/07 → 9/10/07

ASJC Scopus subject areas

Information Systems
Control and Systems Engineering

Access to Document

10.1109/FDTC.2007.4318991

Cite this

Stern, R., Joshi, N., Wu, K., & Karri, R. (2007). Register transfer level concurrent error detection in elliptic curve crypto implementations. In Proceedings Workshop on Fault Diagnosis and Tolerance in Cryptography, FDTC 2007 (pp. 112-119). Article 4318991 (Proceedings Workshop on Fault Diagnosis and Tolerance in Cryptography, FDTC 2007). https://doi.org/10.1109/FDTC.2007.4318991

Register transfer level concurrent error detection in elliptic curve crypto implementations. / Stern, Richard; Joshi, Nikhil; Wu, Kaijie et al.
Proceedings Workshop on Fault Diagnosis and Tolerance in Cryptography, FDTC 2007. 2007. p. 112-119 4318991 (Proceedings Workshop on Fault Diagnosis and Tolerance in Cryptography, FDTC 2007).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Stern, R, Joshi, N, Wu, K & Karri, R 2007, Register transfer level concurrent error detection in elliptic curve crypto implementations. in Proceedings Workshop on Fault Diagnosis and Tolerance in Cryptography, FDTC 2007., 4318991, Proceedings Workshop on Fault Diagnosis and Tolerance in Cryptography, FDTC 2007, pp. 112-119, 4th International Workshop on Fault Diagnosis and Tolerance in Cryptography, FDTC 2007, Vienna, Austria, 9/10/07. https://doi.org/10.1109/FDTC.2007.4318991

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abstract = "In this paper we present an Register Transfer Level (RTL) Concurrent Error Detection (CED) technique targeting hardware implementations of Elliptic Curve Cryptography (ECC). The proposed mixed hardware-and time-redundancy based CED techniques use the mathematical properties of the underlying Galois Field as well as the ECC primitives to detect both soft errors and permanent faults with low area overhead. Results for sequential implementations of GF multiplication and inverse operations yielded an area overhead of 30% and a time overhead of 120%.",

author = "Richard Stern and Nikhil Joshi and Kaijie Wu and Ramesh Karri",

year = "2007",

doi = "10.1109/FDTC.2007.4318991",

language = "English (US)",

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AB - In this paper we present an Register Transfer Level (RTL) Concurrent Error Detection (CED) technique targeting hardware implementations of Elliptic Curve Cryptography (ECC). The proposed mixed hardware-and time-redundancy based CED techniques use the mathematical properties of the underlying Galois Field as well as the ECC primitives to detect both soft errors and permanent faults with low area overhead. Results for sequential implementations of GF multiplication and inverse operations yielded an area overhead of 30% and a time overhead of 120%.

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ER -

Register transfer level concurrent error detection in elliptic curve crypto implementations

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