Reliable computing with ultra-reduced instruction set coprocessors

Dan Wang, Aravindkumar Rajendiran, Sundaram Ananthanarayanan, Hiren Patel, Mahesh V. Tripunitara, Siddharth Garg

Research output: Contribution to journalArticlepeer-review


This work presents a method to reliably perform computations in the presence of hard faults and design defects, based on the observation that a single turing-complete instruction can mirror any other instruction's semantics. the authors extend a mips processor with the ULtra-REduced INstruction SEt Coprocessor (URISC). They evaluate the impact of single-upset faults on the instructions that are rendered faulty and the area and performance overhead of using a URISC.

Original languageEnglish (US)
Article number06679035
Pages (from-to)86-94
Number of pages9
JournalIEEE Micro
Issue number6
StatePublished - Nov 1 2014


  • Benchmark testing
  • Decoding
  • Hard faults
  • Instruction sets
  • Microprocessor reliability
  • Multicore processing
  • Network reliability
  • Registers
  • Semantics
  • Turing-complete ISA
  • Ultra-reduced instruction set coprocessor

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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