Reliable computing with ultra-reduced instruction set coprocessors

Dan Wang; Aravindkumar Rajendiran; Sundaram Ananthanarayanan; Hiren Patel; Mahesh V. Tripunitara; Siddharth Garg

doi:10.1109/MM.2013.130

Reliable computing with ultra-reduced instruction set coprocessors

Dan Wang, Aravindkumar Rajendiran, Sundaram Ananthanarayanan, Hiren Patel, Mahesh V. Tripunitara, Siddharth Garg

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

Abstract

This work presents a method to reliably perform computations in the presence of hard faults and design defects, based on the observation that a single turing-complete instruction can mirror any other instruction's semantics. the authors extend a mips processor with the ULtra-REduced INstruction SEt Coprocessor (URISC). They evaluate the impact of single-upset faults on the instructions that are rendered faulty and the area and performance overhead of using a URISC.

Original language	English (US)
Article number	06679035
Pages (from-to)	86-94
Number of pages	9
Journal	IEEE Micro
Volume	34
Issue number	6
DOIs	https://doi.org/10.1109/MM.2013.130
State	Published - Nov 1 2014

Keywords

Benchmark testing
Decoding
Hard faults
Instruction sets
Microprocessor reliability
Multicore processing
Network reliability
Registers
Semantics
Turing-complete ISA
URISC
Ultra-reduced instruction set coprocessor

ASJC Scopus subject areas

Software
Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/MM.2013.130

Cite this

@article{7aa01bdb61574ac78ddbfb074628ce74,

title = "Reliable computing with ultra-reduced instruction set coprocessors",

abstract = "This work presents a method to reliably perform computations in the presence of hard faults and design defects, based on the observation that a single turing-complete instruction can mirror any other instruction's semantics. the authors extend a mips processor with the ULtra-REduced INstruction SEt Coprocessor (URISC). They evaluate the impact of single-upset faults on the instructions that are rendered faulty and the area and performance overhead of using a URISC.",

keywords = "Benchmark testing, Decoding, Hard faults, Instruction sets, Microprocessor reliability, Multicore processing, Network reliability, Registers, Semantics, Turing-complete ISA, URISC, Ultra-reduced instruction set coprocessor",

author = "Dan Wang and Aravindkumar Rajendiran and Sundaram Ananthanarayanan and Hiren Patel and Tripunitara, {Mahesh V.} and Siddharth Garg",

note = "Publisher Copyright: {\textcopyright} 2014 IEEE.",

year = "2014",

month = nov,

day = "1",

doi = "10.1109/MM.2013.130",

language = "English (US)",

volume = "34",

pages = "86--94",

journal = "IEEE Micro",

issn = "0272-1732",

publisher = "IEEE Computer Society",

number = "6",

}

TY - JOUR

T1 - Reliable computing with ultra-reduced instruction set coprocessors

AU - Wang, Dan

AU - Rajendiran, Aravindkumar

AU - Ananthanarayanan, Sundaram

AU - Patel, Hiren

AU - Tripunitara, Mahesh V.

AU - Garg, Siddharth

PY - 2014/11/1

Y1 - 2014/11/1

N2 - This work presents a method to reliably perform computations in the presence of hard faults and design defects, based on the observation that a single turing-complete instruction can mirror any other instruction's semantics. the authors extend a mips processor with the ULtra-REduced INstruction SEt Coprocessor (URISC). They evaluate the impact of single-upset faults on the instructions that are rendered faulty and the area and performance overhead of using a URISC.

AB - This work presents a method to reliably perform computations in the presence of hard faults and design defects, based on the observation that a single turing-complete instruction can mirror any other instruction's semantics. the authors extend a mips processor with the ULtra-REduced INstruction SEt Coprocessor (URISC). They evaluate the impact of single-upset faults on the instructions that are rendered faulty and the area and performance overhead of using a URISC.

KW - Benchmark testing

KW - Decoding

KW - Hard faults

KW - Instruction sets

KW - Microprocessor reliability

KW - Multicore processing

KW - Network reliability

KW - Registers

KW - Semantics

KW - Turing-complete ISA

KW - URISC

KW - Ultra-reduced instruction set coprocessor

UR - http://www.scopus.com/inward/record.url?scp=84919614917&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84919614917&partnerID=8YFLogxK

U2 - 10.1109/MM.2013.130

DO - 10.1109/MM.2013.130

M3 - Article

AN - SCOPUS:84919614917

SN - 0272-1732

VL - 34

SP - 86

EP - 94

JO - IEEE Micro

JF - IEEE Micro

IS - 6

M1 - 06679035

ER -

Reliable computing with ultra-reduced instruction set coprocessors

Abstract

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this