Reliable integrity checking in multicore processors

Arun K. Kanuparthi, Ramesh Karri

Research output: Contribution to journalArticle

Abstract

Security and reliability have become important concerns in the design of computer systems. On one hand, microarchitectural enhancements for security (such as for dynamic integrity checking of code at runtime) have been proposed. On the other hand, independently, microarchitectural enhancements for reliability to detect and tolerate natural faults have also been proposed. A fault in these security enhancements due to alpha particles or aging might potentially pass off maliciously modified instructions as safe, rendering the security enhancements useless. Deliberate fault attacks by attackers can be launched to disable the security enhancements and then launch the well-known security attacks that would otherwise have been detected by these enhancements. We report an integrated microarchitecture support for security and reliability in multicore processors. Specifically, we add integrity checkers to protect the code running on the multiple cores in a multicore processor. We then adapt these checkers to check one another periodically to ensure reliable operation. These checkers naturally can check the other parts of the core. The average performance, power, and area costs for these security-reliability enhancements are 6.42%, 0.73%, and 0.53%, respectively.

Original languageEnglish (US)
Article number10
JournalACM Transactions on Architecture and Code Optimization
Volume12
Issue number2
DOIs
StatePublished - May 1 2015

Keywords

  • Hardware security
  • Microarchitecture support for security and reliability

ASJC Scopus subject areas

  • Software
  • Information Systems
  • Hardware and Architecture

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