Retiming scan circuit to eliminate timing penalty

Ozgur Sinanoglu, Vishwani D. Agrawal

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Scan design has a performance penalty that affects the critical path delay by an added fanout at the origin and a multiplexer at the destination. This problem is outlined in a recent paper [10], which also proposes a solution. The purpose of the present work is to provide a retiming solution. Retiming of a synchronous sequential circuit is a transformation that moves flip-flops through combinational logic without altering the function. We move the destination flip-flop of a critical path backward through its scan multiplexer. This splits the flip-flop into three, one on each input of the multiplexer. First of these is the original flip-flop in the normal data path. The second, called shadow flip-flop, appears only in the scan path. The third flip-flops from all critical paths are replaced by a single flip-flop that generates a delayed scan enable signal for controlling all retimed multiplexers. We further show how the fanout delay at the origin of a critical path can be eliminated by additional retiming. The use of the formally proven retiming transformations preserve both the function of the circuit and its scan operation without any change. The retimed scan, therefore, can test DC as well as delay faults. Benchmark results show further timing improvement and reduced hardware overhead compared to previously reported results [10].

Original languageEnglish (US)
Title of host publicationLATW 2012 - 13th IEEE Latin American Test Workshop
DOIs
StatePublished - 2012
Event13th IEEE Latin American Test Workshop, LATW 2012 - Quito, Ecuador
Duration: Apr 10 2012Apr 13 2012

Publication series

NameLATW 2012 - 13th IEEE Latin American Test Workshop

Other

Other13th IEEE Latin American Test Workshop, LATW 2012
CountryEcuador
CityQuito
Period4/10/124/13/12

ASJC Scopus subject areas

  • Safety, Risk, Reliability and Quality

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    Sinanoglu, O., & Agrawal, V. D. (2012). Retiming scan circuit to eliminate timing penalty. In LATW 2012 - 13th IEEE Latin American Test Workshop [6261252] (LATW 2012 - 13th IEEE Latin American Test Workshop). https://doi.org/10.1109/LATW.2012.6261252