Reusing the IEEE 1500 design for test infrastructure for security monitoring of Systems-on-Chip

Jerry Backer; David Hely; Ramesh Karri

doi:10.1109/DFT.2014.6962098

Reusing the IEEE 1500 design for test infrastructure for security monitoring of Systems-on-Chip

Jerry Backer, David Hely, Ramesh Karri

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Systems-on-chip (SoCs) are vulnerable to attacks by malicious software and hardware trojans. This work explores if the Design for Test (DfT) infrastructure in SoCs can tackle these security threats with minimum hardware overhead. We show that the observability and plug-and-play features of the IEEE 1500 DfT can be used for scalable security monitoring in SoCs. Existing SoC security countermeasures can reuse the DfT-based security architecture to detect software and hardware attacks. The proposed DfT reuse imposes negligible hardware and performance overheads and doesn't require modifications to the SoC.

Original language	English (US)
Title of host publication	Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	52-56
Number of pages	5
ISBN (Electronic)	9781479961559
DOIs	https://doi.org/10.1109/DFT.2014.6962098
State	Published - Nov 18 2014
Event	27th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2014 - Amsterdam, Netherlands Duration: Oct 1 2014 → Oct 3 2014

Publication series

Name	Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
ISSN (Print)	1550-5774

Other

Other	27th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2014
Country/Territory	Netherlands
City	Amsterdam
Period	10/1/14 → 10/3/14

ASJC Scopus subject areas

General Engineering

Access to Document

10.1109/DFT.2014.6962098

Cite this

Backer, J., Hely, D., & Karri, R. (2014). Reusing the IEEE 1500 design for test infrastructure for security monitoring of Systems-on-Chip. In Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (pp. 52-56). Article 6962098 (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DFT.2014.6962098

Reusing the IEEE 1500 design for test infrastructure for security monitoring of Systems-on-Chip. / Backer, Jerry; Hely, David; Karri, Ramesh.
Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. Institute of Electrical and Electronics Engineers Inc., 2014. p. 52-56 6962098 (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Backer, J, Hely, D & Karri, R 2014, Reusing the IEEE 1500 design for test infrastructure for security monitoring of Systems-on-Chip. in Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems., 6962098, Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Institute of Electrical and Electronics Engineers Inc., pp. 52-56, 27th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2014, Amsterdam, Netherlands, 10/1/14. https://doi.org/10.1109/DFT.2014.6962098

Backer J, Hely D, Karri R. Reusing the IEEE 1500 design for test infrastructure for security monitoring of Systems-on-Chip. In Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. Institute of Electrical and Electronics Engineers Inc. 2014. p. 52-56. 6962098. (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems). doi: 10.1109/DFT.2014.6962098

Backer, Jerry ; Hely, David ; Karri, Ramesh. / Reusing the IEEE 1500 design for test infrastructure for security monitoring of Systems-on-Chip. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. Institute of Electrical and Electronics Engineers Inc., 2014. pp. 52-56 (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems).

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Reusing the IEEE 1500 design for test infrastructure for security monitoring of Systems-on-Chip

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