TY - GEN
T1 - Revisiting logic locking for reversible computing
AU - Limaye, Nimisha
AU - Yasin, Muhammad
AU - Sinanoglu, Ozgur
N1 - Publisher Copyright:
© 2019 IEEE.
PY - 2019/5
Y1 - 2019/5
N2 - Analogous to CMOS circuits, we can expect attacks such as integrated circuit (IC) counterfeiting, piracy through reverse engineering (RE) or over-production, and insertion of hardware Trojans to be launched on emerging class of reversible circuits, which is a promising alternative to standard CMOS technology. In this paper, we explore the possibility of securing reversible circuits against IP piracy and RE attacks using state-of-the-art logic locking techniques. Our security analysis reveals that applying existing techniques as is on reversible circuits creates new vulnerabilities due to inherent reversible properties. We propose low overhead (around 0.013x for gate count, 0.0004x for T-count and 0.02x for quantum cost on average) defense strategies that overcome these vulnerabilities and protect the circuits from all known attacks.
AB - Analogous to CMOS circuits, we can expect attacks such as integrated circuit (IC) counterfeiting, piracy through reverse engineering (RE) or over-production, and insertion of hardware Trojans to be launched on emerging class of reversible circuits, which is a promising alternative to standard CMOS technology. In this paper, we explore the possibility of securing reversible circuits against IP piracy and RE attacks using state-of-the-art logic locking techniques. Our security analysis reveals that applying existing techniques as is on reversible circuits creates new vulnerabilities due to inherent reversible properties. We propose low overhead (around 0.013x for gate count, 0.0004x for T-count and 0.02x for quantum cost on average) defense strategies that overcome these vulnerabilities and protect the circuits from all known attacks.
KW - Equivalence checker
KW - IP piracy
KW - Reverse engineering
KW - Reversible circuits
KW - Stripped functionality logic locking
UR - http://www.scopus.com/inward/record.url?scp=85071185539&partnerID=8YFLogxK
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U2 - 10.1109/ETS.2019.8791550
DO - 10.1109/ETS.2019.8791550
M3 - Conference contribution
AN - SCOPUS:85071185539
T3 - Proceedings of the European Test Workshop
BT - Proceedings - 2019 IEEE European Test Symposium, ETS 2019
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2019 IEEE European Test Symposium, ETS 2019
Y2 - 27 May 2019 through 31 May 2019
ER -