Shrinking feature sizes have magnified deep sub-micron effects, resulting in integrated circuits prone to timing-related defects. Stringent test quality requirements have therefore mandated the use of at-speed testing schemes, however, excessive switching activity during the launch operation may result in yield loss. In this paper, we propose a design partitioning technique that can reduce power dissipation during launch and capture operations in the launch-off-shift (LOS) based at-speed testing scheme. As opposed to the existing partitioning techniques, the proposed low-power framework enables the re-use of a (compact and high quality) set of patterns generated by a conventional power-unaware LOS ATPG tool as is, which can be applied in a low power manner. To tackle this challenge, we derive partitioning rules as well as the non-intrusive DfT support needed, enabling the transformation of power-thriftless patterns into power-frugal ones, while retaining pattern count and test quality (fault and ancillary defect coverage) intact.