R<sup>2</sup>Cache: Reliability-aware reconfigurable last-level cache architecture for multi-cores

F. Kriebel, A. Subramaniyan, S. Rehman, S.J.B. Ahandagbe, M. Shafique, J. Henkel

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Original languageUndefined
Title of host publication2015 International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2015
DOIs
StatePublished - 2015

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